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Processor Organization
Datapath Design
21 June 2007
Review
• Construction of the ALU
– Building blocks (digital design gates)
– Modular design
• Multiplexor chooses operation
• All operations are performed in parallel
– Carry lookahead adder
• Computer arithmetic
– Finite precision
– Laws of algebra do not always hold
– Integers: two’s complement representation
– Floating point: IEEE 754 standard
Overview
• Computer organization (microarchitecture)
• Processor organization
– Datapath
– Control
– Register file
• Processor implementation overview
• Clocking methodologies
• Sequential circuits
– Latches
– Registers
Processor Performance
CPU time = IC * CPI * Cycle time
Program
Compiler
ISA
Microarchitecture
Hardware
Computer Organization
Address Bus
Memory
Processor Data Bus
Control Bus Subsystem
I/O . . . I/O
device device
I/O Subsystem
The Processor
• Processor (CPU)
– Active part of the computer
– Does all the work
• Data manipulation
• Decision-making
• Datapath
– Hardware that perform all required operations
– ALU + registers + internal buses
– The brawn
• Control
– Hardware which tells the datapath what needs to be done
– The brain
Processor Organization
Address bus Data bus
Control bus signals
Control signals
Control
Unit Data values
Registers
Control signals
Instruction rd Data
memory
rs Address
PC
+4 Data
imm
Opcode, funct
Controller
Timing diagrams
clock
State Combinational
element logic
NOR SR Latch
State 0 State 1
S - set
Inputs Outputs: Q and Q
R - reset
Clocked SR Latch
Clocked D Latch
D
C
Setup time
D
hold time
Read ports
Write port
Register File Read Ports
Register File Write Ports
Conclusions
• Datapath performs work of computation
• Building blocks for datapath
– ALU: Performs work of computation
– Register File: Data I/O from registers
• Register file implemented with D flipflops,
multiplexers, and decoder
– Clocked (synchronous) logic circuits
– Write-enabled data transfer into registers
– No need to protect data transfer from registers
Anticipate the Mid-Semester
Break!!
New Topic –Datapath Design
• Datapath implements fetch-decode-execute
• Design Methodology
Determine instruction classes and formats
Build datapath sections for each instr.fmt.
Compose sections to yield MIPS datapath
+
4
PC Read Addr
Instruction
fetch
Instruction
Memory
R-format Datapath
• Format: opcode r1, r2, r3
ALU op
Register 3
File
Read Reg 1 Read
Instruction
Data 1 Zero
Read Reg 2
Write ALU
Register Read
Write Data Data 2
Result
Register
Write
Load/Store Datapath Issues
• lw $t1, offset($t2)
– Memory at base $t2 with offset
– lw: Read memory, write into register $t1
– sw: Read from register $t, write to memory
• Address computation – ISA says:
– Sign-extend 16-bit offset to 32-bit signed value
MemWrite
16 32
Sign
Address Extend
Read data
Data
Write data Memor
y 1101 … 0011
1111 1111 1111 1111
MemRead 1101 … 0011
Load/Store Datapath Actions