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P-N junction – Built-in-Potential


Under equilibrium

Since E = −dV/dx,
Dividing both sides by p &
taking the integral,

where pn and pp are the hole concentrations at x1 and x2

Also, Dp/μp = kT/q = VT

Built-in-Potential developed across the depletion region is,


=VT
Built-in-potential equation can be re-arranged as,

subscript ‘e’ denotes equilibrium conditions

Under FB, the potential barrier is lowered by the applied voltage

subscript f denotes forward bias

minority carrier concentration on the ‘p’ side rises rapidly


majority carrier concentration remains relatively constant

The statement applies to the n side as well


Carrier profile in equilibrium Carrier profile under FB

As the junction goes from equilibrium to FB,


np and pn increases
Results in proportional increase in diffusion
current
Change in the hole concentration on the n side is;
Similarly, for the electron concentration on the p side

We have =VT 

Increase in the minority carrier concentration must result


in rise in diffusion currents by a proportional amount

IS the “reverse saturation


current” and is given by
‘A’  cross section area of the device
Ln and Lp  electron and hole “diffusion lengths”
Problem: A silicon pn junction has
NA = 2 × 1016 cm−3 and
ND = 4 × 1016 cm−3,
A = 100μm2,
Ln = 20μm,
Lp = 30μm,
ni(T = 300 K) = 1.08 × 1010 cm−3,
q =1.6 ×10−19 C,
Dn = 34 cm2/s and
Dp = 12 cm2/s
Determine
(i) built-in potential at room temperature
(ii) hole & electron concentrations on the two sides
(iii) IS
(768mV)

pp ≈ NA pn ≈ ni2/ND

np ≈ ni2/NA

nn ≈ N D (1.77 × 10−17A)
BJT can modeled as a voltage-dependent current source

Vout = −RLI1  Vout = −KRLVin

If, KRL>1, circuit act as an amplifier

Negative sign indicates input & output are out of phase by 180º

Voltage gain AV = Vout/Vin= −KRL


AV depends on
K of the controlled current source
load resistor
K signifies how strongly V1 controls I1
emitter “emits” charge carriers
collector “collects” them
base controls the flow of carriers from emitter to collector

Emitter area < Collector area

Emitter doping > Collector doping

Hence, E and C terminals cannot be interchanged


active region
base-emitter junction is forward biased (VBE > 0)
base-collector junction is reverse-biased (VBC < 0)

A intuitive model could be

forward biased D1 carries a current


reverse biased D2 does not
current flow from the B to E
no current through the collector terminal

BJT cannot operate as a voltage-controlled current source?


With E-B junction forward-biased,
electrons flow from E to B
holes flow from B to E

For proper transistor operation,


former current must be > the later

To achieve this
emitter is doped much heavily than base

Since base region is thin,


most of the electrons reach the edge of the C-B depletion
region before getting recombined in the base region

Reverse biased C-B junction sweeps the electrons into the


collector region
resulting in a current through reverse biased C-B junction
Carrier profiles

Electron density is very high at x = x1

As electrons arriving at x = x2 is swept


away,
the density of electrons falls to zero at
x = x2

Profile of electron density in the base


provides a gradient for the diffusion of
electrons
Collector Current
With emitter doping of NE &
base doping of NB

Concentration of electrons at x = x1 is given by;

We also have the expression for the built in potential as;

We can write;
Current Density

Multiplying the current density by the emitter cross-


section area (AE),
and then substituting for Δn(x1)
and changing the sign to obtain the conventional current,
we obtain

In analogy with the diode current equation and


assuming exp(VBE/VT)>>1, we write

Where
BJT indeed operates as a voltage controlled current source

As long as the device remains in the active mode, current


does not depend on the collector voltage

For a fixed VBE, the device draws a constant current, acting


as a current source
Q1 and Q2 are identical and operate in the active mode with V 1
= V2. Determine the current IX

BJT are in parallel  IX = IC1 + IC2

BJT are identical and biased identically



 Collector current of a single transistor having an emitter
area of 2AE

 Higher current rating can be achieved either by having

a single BJT of larger area


or by connecting BJTs in parallel which are smaller in area
Q1 and Q2 are identical and operate in the active mode.
Determine V1 − V2 such that IC1 = 10IC2.

 VBE of Q1 must rise by ≈ 60mV (at T = 300 K) to result in tenfold


increase in the current

 The device exhibits a 60 mV/decade characteristic

 In general, an n-fold change in IC translates to a change of


VTln(n) in VBE

 For typical collector current levels,


base-emitter voltage is considered constant and  0.8V
Discrete BJT have a typical area of 500μm×500μm, whereas
modern integrated devices have a typical area of 0.5μm×0.2μm.
Assuming other device parameters are identical, determine the
difference between VBE of two such transistors for equal collector
currents.

Denoting VBE of discrete & integrated circuit BJT as VBEint & VBEdis,

AE2/AE1=2.5×106  VBEint - VBEdis= 83mV at room temperature

In practice this difference is in the range of 100 to 150mV

Typically, VBEdis = 700mV and VBEint = 800mV


In the circuit assuming IS=5×10−16A determine the output voltage.

VBE=750mV, VT=26mV, IS=5×10−16A

 IC=1.69mA

Drop across RL=ICRL=1.69mA×1k = 1.69V

Vout = 3-1.69 = 1.31V


Electrons injected by the emitter, as they travel through the base,
some may “recombine” with the holes resulting in a base current

 We can view IB as a constant fraction of IE


or a constant fraction of IC

 It is common to write IC = βIB


β is called the “current gain” of the transistor

 β of npn transistors typically ranges from 50 to 200

On applying the KCL to the transistor, IE = IC + IB = IC(1 + 1/β)

We can also write

Denoting We can write, IC = IE


For =100, we get =0.99, thus, IC  IE.
A bipolar transistor having IS = 5×10−16A is biased in the active
region with VBE = 750mV. If the current gain () varies from 50 to
200 due to manufacturing variations, calculate the minimum and
maximum terminal currents of the device.

IC = ISexp(VBE/VT) = 1.685mA

IB varies from IC /200 to IC /50  8.43μA < IB < 33.7μA

IE varies from IC+IBmin to IC+IBmax 1.693mA < IE < 1.719mA

Even though IB varies to a large extent,


IE varies only by a small fraction
Since the B-E junction is forward-biased in the active mode,
We can place a diode between the B and E terminals

Since the current drawn from the collector and flowing into
the emitter depends only on VBE

We add a voltage-controlled current source between the


collector and the emitter
The resulting BJT model is;

As long as the device operates in the active mode, the model


can be used for arbitrarily large voltage & current changes in
the transistor giving the name “Large-Signal Model”
To ensure the current flowing through the diode = I C/β

Since IB=IC/=[ISexp(VBE/VT)]/,

B - E junction can be modeled by a diode whose


cross section area is 1/β times that of the actual emitter area
In the circuit IS,Q1 = 5×10−17A and VBE = 800mV. Assume β = 100.
(a) Determine the transistor terminal currents and voltages
and verify that the device indeed operates in the active mode.
(b) Determine the maximum value of RC that permits operation
in the active mode.
IC = ISexp(VBE/VT) = 1.153mA

IB = IC/ = 11.53A

IE = IB + IC = 1.165mA

Collector voltage VX=2-ICRC = 1.424V

Since VX>VBE; the B-E junction is reverse biased


 the transistor operates in the active mode

If RC increases, the voltage at node X drops


if VX drops to 800mV the junction will be just in active region

 There is upper limit on resistance (RC)  on voltage gain


I/V Characteristics
(i) IC versus VBE with B-C junction reverse biased

plot is similar to diode characteristic and is independent of VCE

(ii) IC for a given VBE with varying VCE (VCE > VBE)

For a constant VBE, IC is constant and hence the characteristic is


a horizontal line
For different values of VBE, the characteristic moves up or down

As IB=IC/ & IE=[(1+)/)]IC, their plot will be similar to plot of IC


How best is the BJT ‘as a voltage-dependent current source’?

I1 = KV1 as K increases a given input voltage yields a larger


output current

For BJT, we need to know,

if a signal changes VBE by a small amount, how much change is


produced in the collector current?

Denoting the change in IC by ΔIC, we can represent the “strength”


of the device by ΔIC/ΔVBE

Ratio ΔIC/ΔVBE approaches dIC/dVBE for very small changes and is


called the trans conductance (gm) of the BJT
gm=dIC/dVBE

For a BJT, we can write,

As IC increases, the transistor becomes a better amplifying device

If IC = 1mA, with VT = 26 mV,

we get, gm = 0.0385 −1
= 0.0385℧
= 0.038A/V
= 0.038S
gm could be visualized as the slope of IC -VBE characteristic at a given
collector current IC0 and the corresponding base-emitter voltage VBE0

if VBE experiences a small change ±ΔV around VBE0,


then the collector current displays a change of ±g mΔV around IC0,
where gm = IC0/VT

IC0 must be chosen according to the required g m resulting in the required


gain

In such a case, the transistor is said to be “biased” at a collector current


of IC0,
In the circuit what happens to the transconductance of Q1 if the
area of the device is increased by a factor of n?

Since IS∝AE, IS is multiplied by a factor ‘n’

 IC= IS exp(VBE/VT) also rises by a factor of n

 Transconductance (gm = IC0/VT) increases by a factor n

Could be treated as ‘n’ identical transistors with emitter area AE,


each carrying a collector current of IC0 connected in parallel
In the context of the IC -VCE characteristics with VBE as a parameter

A change of ΔV in VBE results in a greater change in IC

for operation around IC2 than


around IC1 because gm2 > gm1

gm=IC/VT suggests that gm is function of IC than on IB

If IC remains constant but if β varies,


Small-Signal Model

With a small-signal model for transistors


It could be reduced to a linear device

change in VBE while VCE is constant

We have, ΔIC = gmΔVBE

 Above equation indicates that a voltage-controlled


current source of gmΔVBEmust be connected between C & E

Denoting ΔVBE by vπ , we write ΔIC = gmvπ


With change in VBE, ΔIB = ΔIC/β = gmΔVBE/β

With ΔVBE, the current flowing between E – B loop changes by


(gm/β)ΔVBE

 Could be modeled by a resistor ‘rπ ’ placed between B & E


terminal with rπ = ΔVBE/ΔIB = β/gm
Apply a voltage change at collector with respect to the
emitter

For a constant VBE, ΔVCE has no effect on IC or IB because


IC = IS exp(VBE/VT)
IB = IC /β

 No change is required in the model developed


gm=IC/VT and rπ = β/gm = βVT/IC
depend on the bias current of the device

High collector bias current  greater gm


lower rπ
In the circuit v1 represents the signal generated by a microphone,
IS = 3×10−16A, β = 100, and Q1 operates in the active mode.
(a) If v1 = 0, determine the small-signal parameters of Q1.
(b) If the microphone generates a 1mV signal, how much change is
observed in the collector and base currents?

(a) IC = IS exp(VBE/VT) = 6.92mA


gm = IC/VT = 0.266 -1
rπ = β/gm = 376
 small-signal equivalent circuit is
(b) From circuit

vπ = v1

 ΔIC = gmv1 = 1mV×0.266 = 0.266mA

ΔIB = v1/rπ = 1mV/375 = 2.67μA

Or ΔIB = ΔIC/β = 2.67μA


Practically the circuit is of no use

Microphone signal produces a change in IC, but the


resulting current flows through the 1.8V battery producing
no output

If the collector current flows through a resistor, a useful


output could be provided

Resistor could be replaced by a speaker,


the speaker resistance acts as the resistor
Early Effect

We have, Voltage gain AV = Vout/Vin= −KRL

If RC increases, so does the voltage gain

Does this mean that, if RC , then the gain  ?

Is there any mechanism that limits the maximum gain?

“Early effect” is one of the non-ideality in the device that


can limit the gain of amplifiers
Our assumption was “IC is independent VCE”

reverse bias across the C-B junction results in depletion region

If VCE is raised to VCE2, depletion region widens

 effective base width (WB) decreases

 the slope of the profile increases

 collector current increases

As this phenomenon is discovered by Early,


it is known as Early Effect
IC and VCE are related by

Where WB is assumed to be constant

Factor, 1 + VCE/VA, models the Early Effect

VA is called the Early Voltage

For a constant VCE, IC - VBE relation remains exponential


but with a somewhat greater slope
For a constant VBE, the IC − VCE characteristic displays a
nonzero slope

If VCE<<VA, we get IC ≈ IS exp(VBE/VT), is valid for most cases

Variation of IC with VCE


 BJT does not operate as an ideal current source
 BJT could be viewed as a two-terminal device
but with a current that varies to some extent with V CE
The large-signal model is modified as,

where

IB is independent of VCE and still given by VBE


small-signal model

 controlled current source remains unchanged

Similarly,
Considering IC varies with VCE,

small-signal model contains rO representing the Early Effect

Known as “output resistance


Both rπ and rO are inversely proportional to IC
A transistor is biased at a collector current of 1mA.
Determine the small-signal model if β = 100 and V A = 15V

gm=IC/VT=0.038 -1

rπ=/gm=2.63k

ro=VA/IC = 15 k
BJT has IC = 1mA with VCE = 2V. Determine VBE if VA =∞ and
VA = 20 V. Assume IS = 2×10−16A

VA = ∞  VBE=VTln(IC/IS) = 26×10−3ln(1×10−3/2×10−16) = 760.25mV

VA = 20V VBE= 757.78mV

 VBE = 760.25mV-26mV(2/20) = 757.65mV


Saturation Mode

When VCE falls below VBE; VBC becomes > 0

 B-C junction gets forward biased

 both the junction are forward biased


transistor said to be biased in the “saturation region”

Suppose if VBC = 200mV, the forward biased C-B junction


carries an extremely small current

BJT continues to operate as in the active mode,


device is said to be in “soft saturation”
If VCE drops further, the B-C junction experiences greater
forward bias, carrying a significant current

 large number of holes must be supplied to the base


terminal;
as a consequence it looks as if β is reduced

 Heavy saturation leads to a sharp rise in the base current


and hence a rapid fall in β
BJT is biased with VBE = 750mV and has β = 100. How much B-C
forward bias can the device tolerate if β must not degrade by
more than 10%? For simplicity, assume B-C and B-E junctions
have identical structures and doping levels
If the C-B junction is forward-biased such that it carries a current
equal to one-tenth of the nominal base current, IB,

β degrades by 10%

 Since IB = IC/ = IC /100,


the B-C junction should carry a current not more than IC /1000

 If VBE = 750mV gives a collector current of IC, we should


determine B-C voltage that results in a current of IC /1000
Assuming identical B-E and B-C junctions, we have,

VBE − VBC =VT ln(IC/IS) - VT ln(IC/1000IS)


= VT ln1000

= 180mV

 VBC = 570mV
The BJT model can be re-constructed as

Model includes a base-collector diode

Net collector current decreases as the device enters saturation


because part of the controlled current IS1 exp(VBE/VT) is now
supplied by the B-C diode

 IC begins to fall for VCE less than V1


In the deep saturation, the C-E voltage approaches a
constant value called VCEsat (0.2V)

Under this condition, the transistor bears no resemblance


to a controlled current source and can be modeled as a
battery tied between C and E
For the circuit determine the relationship between RC and VCC
that guarantees operation in soft saturation or active region

In soft saturation, IC = IS exp(VBE/VT) and


VC must not fall below the VB by more than 200 mV

 (VCC − ICRC) must be ≥ VBE − 200mV

 VCC ≥ ICRC + (VBE − 200 mV)

 For a given value of RC, VCC must be sufficiently large


so that VCC − ICRC still maintains a reasonable collector voltage
A transistor with IS = 6 × 10−16 A must provide a gm of 1/13.
What base-emitter voltage is required?

gm=IC/VT

In the circuit depicted IS1 = 2IS2 = 4 × 10−16 A. If β1 = β2 = 100


and R1 = 5 k, compute VB such that IX = 1 mA.

IX=IS1exp(VBE/VT)  VBE=
IY=IS2exp(VBE/VT) =

IB1=IX/ 1 =
IB2=IY/ 2 =

VB=(IB1+IB2)R1+VBE =
In the circuit determine the maximum value of V CC that
places Q1 at the edge of saturation. Assume I S = 3 × 10−16 A.
Collector Voltage VC = Base Voltage VB
VCC=ICRC + VC IC = ISexp(VB/VT)
VCC= RCISexp(VB/VT) + VB

Determine the operating point and the small-signal model


of Q1. Assume IS = 8 × 10−16 A, β = 100, and VA =∞.
IB=10A = [ISexp(VBE/VT)]/ β  VBE=
IC= βIB = gm= Ic/VT =
IE=IC+IB = r= /gm =
r0= 
Base Voltage VB= VBE + IE1k =
Collector Voltage VC = 2V VCB= VC - VB =
In the circuit, I1 is a 1mA ideal current source and IS = 3×10−17
A. (a) Assuming VA =, determine VB such that IC = 1 mA.
(b) If VA = 5 V, determine VB such that IC = 1mA for VCE=1.5 V.

(a) 1mA= 3× 10−17 exp(VB/VT)  VB=

(b)  VB =

For the circuit, calculate the maximum value of VCC that


produces a forward bias of VBC=200mV. Assume IS = 7×10−16A
and VA =  . V =I 1k = 200mV  I = 0.2mA
BC C C

From the Figure VBE=VCC

0.2mA= 7×10−16 exp(VCC/VT)  VCC=


In the circuit IS1 = IS2 = 3×10−16 A.
(a) Calculate VB such that IX = 1 mA
(b) With the value of VB found in (a), find IS3 such that IY = 2.5 mA

IX = 2IS1 exp(VB/VT)  VB=

IY = IS3 exp(VB/VT)  IS3=

In the circuit Calculate VX if IS = 6×10−16 A


1.5=VBE + (IC+IB) 1k
1.5VBE + IC 1k
1.5VBE + IS exp(VBE/VT) 1k
VX IC1k =
In the circuit, n identical transistors are in parallel. IS=5×10−16A
and VA = 8 V for each device, construct the small-signal model
of the equivalent transistor.
Amplifier with a voltage gain of 10 senses a signal generated by a
microphone and applies the amplified output to a speaker

Microphone is modeled as a voltage source having a10mVp-p signal


and a series resistance of 200 .

Speaker is represented by an 8 resistor.

(a) Determine the signal level sensed by the amplifier if the circuit
has an input impedance of 2k or 500.

(b) Determine the signal level delivered to the speaker if the circuit
has an output impedance of 10 or 2
Signal level sensed by the amplifier V1 = Vm[Rin/(Rin+Rm)]

When Rin = 2k; V1 = 0.91Vm  Only 9% loss

When Rin = 0.5k; V1 = 0.714Vm  30% loss

Vout = Vamp[RL/(RL+Ramp)]

When Ramp = 10; Vout = 0.44Vamp  56% loss


When Ramp = 2; Vout = 0.8Vamp  20% loss
Measuring I/O impedances

Set all independent sources in the circuit are set to zero

Apply a voltage source to the two nodes of interest

Measure resulting current

Impedance = VX/IX
Assuming that the transistor operates in the active region,
determine the input impedance.

Input impedance is simply given by

 higher β or
lower IC yield a higher input impedance
Neglecting the Early effect calculate the impedance seen
at the emitter of Q1

Setting Vin and VCC to zero and applying VX at emitter we get,

From the circuit, vπ = −VX

Since rπ = β/gm >> 1/gm, we get Rout ≈ 1/gm


Calculate the impedance with respect to collector of Q1

Setting Vin to zero and applying VX at Collector we get,

Since vπ = 0, gmvπ = 0

 Rout = rO

 If Early effect is neglected, Rout = 


With Emitter grounded,
looking into the base,
we see rπ

With emitter grounded,


looking into the collector,
we see rO

With base grounded,


Early effect is neglected,
looking into the emitter,
we see 1/gm
In the circuit shown IS=6×10−16A and the peak value of the
microphone signal is 20 mV, determine the peak value of the
output signal.

Note that there is no base bias

When Vin =20mV; ΔIC=1.29×10−15A

Output voltage = RCIC = 1.29×10−12V

With no biasing, gm0  there is no gain


Connecting base to VCC gives required base bias

Base voltage remains constant at VCC prohibiting any


change introduced by the microphone

With VBE = VCC = 2.5 V, large current flows in the transistor


VCC= RBIB + VBE

To avoid saturation
For the circuit determine the collector bias current to
avoid. β = 100 and IS = 10−17 A. Verify that Q1 operates in
the active region.
Assuming VBE = 800mV

VCEVBE BJT is at the edge of

saturation modes
Because VCC − VBE determines IB,

at low values of VCC, bias is more sensitive to VBE


variations

IC depends on β,
In the previous example, if β increases from 100 to 120,
IC rises to 1.98 mA
and VCE falls to 0.52, driving the transistor to saturation

Hence this bias is rarely used in practice


If the base current is neglected

 As long as IB is negligible, IC is independent of β


In the circuit determine IC. Given IS = 10−17 A and β = 100.
Verify that the base current is negligible and the transistor
operates in the active mode.

VCE = VCC-ICRC = 1.345V

Is the base current negligible?

current flowing through R1 and R2 is


Thevenin's
Equivalent
Circuit is
Calculate IC. Assume β = 100 and IS = 10−17A

With VBE = 750mV

 IB=0.441μA and hence IC=44.1μA


After many iterations, VBE≈766mV and IC=63μA

Exponential dependence of IC on VX leads to considerable bias variations


Biasing with Emitter Degeneration

Neglecting the base current,

Increase VBE  Increase in IE  Increase in VP  decrease in VBE

 Stable operating point


Calculate the bias currents and verify that Q1 operates in the
active mode. Assume β =100 and IS = 5×10−17A. How much does
IC change if R2 is 1% higher than its nominal value?

Using VBE = 800mV,

IE = VP/RE=1mA  IE IC = 1mA

 VBE = 796mV

 initial guess is reasonable

Collector voltage VY =VCC-ICRC=1.5V

Since (VY=1.5V) > (VX=0.9V), BJT is in active region


How much does IC change if R2 is 1% higher than its nominal
value?

 VX = 906mV

Using VBE = 800mV, = 106mV

IE = VP/RE=1.06mA

 IE and hence IC changes only by 6%


This biasing is extensively used in discrete circuits and
occasionally in integrated circuits

Design rules are:


I1>>IB to make the circuit less sensitive to β
VRE must be large to suppress the variations in V X and VBE
RC must be small enough to avoid BJT satuation
Design Procedure

(1) Decide on a collector bias current for a gm and rπ

(2) Based on the expected variations of R1, R2, and VBE, choose a
value for VRE ≈ ICRE, say 200 mV

(3) Calculate VX = VBE + ICRE with VBE = VT ln(IC /IS)

(4) Choose R1 & R2 to provide the required VX & establish I1>> IB


Design the circuit to provide a gm of 1/52. Assume VCC = 2.5V,
β=100, and IS=5×10−17A. Determine the maximum value of RC
gm= IC/VT  IC=0.5mA
IB =IC/=5A
Assuming VRE= 200mV;
VRE =ICRE  RE=400

VBE = VT ln(IC /IS) =778mV

VX  VBE+VRE =978mV
IB =5A

We want, I1>> IB Let, I1 =10IB=50A

 I1=VCC/(R1+R2) = 50A

 R1+R2 = 50k

Also, VX = VCCR2/(R1+R2) = 978mV


 R2 = 19.5k

We have, R1+R2 = 50k


 R1= 30.5k

VCC−RCIC>VX  RC<3k
Redesign the circuit to provide a gm of 1/52. Assume VCC =
2.5V, β=100, and IS=5×10−17A. Determine the maximum value
of RC. Assume VRE= 500mV and I1≥100IB
gm= IC/VT  IC=0.5mA
IB =IC/=5A
Assuming VRE= 500mV;
VRE =ICRE  RE= 1k

VBE = VT ln(IC /IS) =778mV

VX  VBE+VRE =1.278V
IB =5A

We want, I1>> 100IB Let, I1 =500A

 I1=VCC/(R1+R2) = 500A

 R1+R2 = 5k

Also, VX =1.278V = VCCR2/(R1+R2)


 R2 = 2.5k

We have, R1+R2 = 5k


 R1= 2.5k

VCC−RCIC>VX  RC<2.4k
Reduction in RC translates to a lower voltage gain

Smaller values of R1 and R2  low input impedance

Ri Ri1

r= /gm  r=5.2k


Self-Biased Stage

Base voltage is always < Collector voltage


VX = VY − IBRB

Guarantees active mode regardless of


device and circuit parameters

Assuming IB << IC ; IRC  IC  VY = VCC − RCIC

Also, VY = RBIB + VBE = [(RBIC)/β] + VBE

Solving the two equations for IC


Determine the IC and VY. RC=1k, RB=10 k, VCC=2.5V, IS=5×10−17A,
and β = 100. Assuming VBE = 0.8 V. Repeat the calculations for
RC=2k.

= 1.545mA

= 0.807V

VY = RBIB+VBE = 0.955 V

If RC = 2k, with VBE =0.8 V, IC=0.81mA

VBE=0.791V

VY=0.872V
Design Guidelines

VCC−VBE must be >> the uncertainties in the value of VBE

RC must be >> RB/β to lower sensitivity to β

If RC>>RB/β,

we choose 
Design the self-biased circuit for gm=1/13 and VCC=1.8V.
Assume IS=5×10−16A and β = 100.

gm=IC/VT = 1/13  IC=2 mA

 VBE=754mV

 RC=475

 RB=4.75k

VY = VCC-ICRC = 1.8 – 0.95 = 85V


Common-Emitter Topology

Small-signal voltage gain Av = vout/vin

Increase vin  increase in VBE  increase in IC  decrease in vout


 Gain is negative

Av is proportional to gm (hence on IC)and RC


Since lowering the limit to VRC < VCC,

Also BJT requires a minimum VCE = VBE to remain in active mode


Design a CE amplifier with VCC=1.8V and a power budget, P=1mW
while achieving maximum voltage gain. Use VBE=0.8V.

P = ICVCC=1mW  IC = 0.556 mA

Value of RC that places Q1 at the edge of saturation is given by;

Small-signal voltage gain Av


Input of 2-mV p-p results in a 77-mVpp output, forward-biasing
the B-C junction for half of each cycle

As long as Q1 remains in soft saturation (VBC > 400 mV), circuit


amplifies properly
more aggressive design is to allow BJT to operate in soft
saturation, e.g., VCE ≈ 400mV

 RC≤ 2.52 k  Voltage gain Av = −53.9

Input of 2-mV p-p signal gives 107.8-mV p-p output, driving BJT
into heavy saturation

The circuit suffers from a trade-off between voltage gain


and voltage headroom
 Rin decreases as IC increases

 Rout trades with AV = −gmRC


A CE stage must have input impedance of Rin
output impedance of Rout.
What is the voltage gain of the circuit?

Rin = rπ = β/gm Rout = RC

Av = −gmRC = −β Rout/Rin

if I/O impedances are specified,


then the voltage gain is automatically set
CE stage with Early Effect

Av = −gm(RC ||rO)

 Rin = r

 Rout = ro//RC
The circuit is biased with a IC of 1 mA and RC = 1 k. If β = 100 and
VA=10 V, determine the small-signal voltage gain and the I/O
impedances.
CE stage with Early Effect
No external load; RC  

gmrO is maximum voltage gain provided by a single transistor

Is called the “intrinsic gain”

We have, gm = IC/VT and rO = VA/IC  |Av| = VA/VT

Intrinsic gain is independent of the bias current

For modern integrated BJT, VA= 5 V  |Av| = 192


“current gain,” AI = iout/iin

= gm/r = 

“current gain,” AI = iout/iin


= [gm/r] ro/(ro+RC)

= ro/(ro+RC)
CE Stage With Emitter Degeneration


With β>>1, we can assume gm>>1/rπ 

 gain falls by a factor of 1 + gmRE

Gain equation can be re-arranged as,

 “the gain of the degenerated CE stage is equal to the total load


resistance seen at the collector to ground divided by 1/gm
plus the total resistance placed in series with the emitter”
If gmRE>>1 Av = −RC/RE  Av is independent of BJT parameters
Determine the voltage gain
A CE stage IC = 1mA, AV = 20 no emitter degeneration and 10 with
degeneration, determine RC , RE, and the I/O impedances. Assume
β = 100

With no emitter degeneration, Av = 20  gmRC = 20

Also, gm = IC/VT = 0.03846℧

 RC = 520

With degeneration = 10

 1 + gmRE = 2  RE = 26

Rin = rπ + (1+β) = [β/gm] + (1+β)RE = 5.26k

Rout = RC = 520
Compute the voltage gain and I/O impedances.
Assume a very large value for C1

For AC analysis capacitor is


replaced by short circuit

Current source is replaced by


open circuit

One additional term in the denominator = RB/(β+1)
A microphone has an output resistance of 1k,
peak signal level of 2 mV.
Design a CE stage that amplifies this signal to 40 mV. Use IC=1 mA,
RE=4/gm and β=100

RB = 1 k gm= 1/26 |Av| = 40/2 = 20

RE = 426 = 104

≈ 2.8 k
Determine the voltage gain and I/O impedances. Assume a very
large value for C1 and neglect Early effect.

Emitter degeneration raises Rout from rO by a factor of 1+ gm(RE||rπ)


For RE >> rπ, we have RE||rπ  rπ

For RE << rπ, we have RE||rπ  RE

Output resistance is boosted by a factor of 1 + gmRE

We sometimes explicitly draw the transistor


output resistance to emphasize its significance
Design a current source having a value of 1 mA and an output
resistance of 20 k. For BJT β=100 and VA=10V. Determine REmin

rO = VA/IC = 10 k

Rout needed = 20k

 Degeneration must raise rO by a factor of 2

Assuming case of RE << rπ ;

 1 + gmRE = 2

 RE = 1/gm = 26 rπ = β/gm = 2.6k >> RE = 26


Calculate the output resistance

We have


Determine the output resistance
CE Stage with Biasing

microphone resistance = 100

 microphone resistance disrupts

the bias of the amplifier

Coupling capacitor C1 overcomes


this problem
What happens if speaker resistance is 8?

VC =VCC(8)/[1k+8] = 8mV

 BJT goes to saturation

Coupling capacitor C2
overcomes this problem

no gain in the circuit


|Av| = gm(RC ||RSpeaker)
How to have degeneration to biasing
but not to the signal?
Design the circuit to satisfy with: IC=1mA, VRE=400mV, AV=20 in
the audio frequency range (20Hz to 20 kHz), Ri > 2k. Assume β=
100, IS=5×10−16, and VCC=2.5V
IC=1mA ≈ IE and VRE=400mV

 RE = 400
For gain to be unaffected by
degeneration;

maximum impedance of C1 << 1/gm

Maximum impedance of C1 occurs at 20Hz;


Let it be < 0.1(1/gm)

VRE = 400mV; VBE = VT ln(IC /IS) = 736mV;  VX = 1.14 V

IB=IC/ = 10μA;

current flowing through R1 and R2 must be > 10IB


to lower sensitivity to β
 current flowing through R1 and R2 = 100μA

Rin = 1.83 does not satisfy the condition Rin > 2 k


Current through R1 and R2 be 5IB = 50μA
Common-Base Topology
Voltage output of an electronic thermometer is 600mV at
room temperature. Design a CB stage amplify the voltage
change with maximum gain. Assume VCC =1.8V, IC=0.2mA,
IS=5×10−17A, and β = 100.

To avoid saturation, VC>VB

maximum voltage drop across RC



generating Vb

Choose I1 ≈ 10IB ≈ 20μA = VCC/(R1 + R2)

 R1 + R2 = 90 k
Input and Output Impedance
With base grounded,
Early effect neglected,
rπ = β/gm >> 1/gm,

looking into the emitter,


we see 1/gm

A C-B amplifier is designed for an input impedance of Rin and an


output impedance of Rout. Neglecting the Early effect, determine
the Av.

We have, Rin = 1/gm  Av = gmRC = Rout/Rin


Rout = RC ,
which on flowing through RC , yields

Voltage gain never exceeds 0.5 if RC ≤ RS


A C-B stage is designed to amplify an RF signal received by a 50
antenna. Determine the required bias current if the Rin must
“match” the impedance of the antenna. Determine AV if the C-B
stage also drives a 50 load. Assume VA =.

Rin= 1/gm = RS = 50

If RC is replaced by a 50 load,

Signal is attenuated by 2  The circuit is not suitable for


driving a 50 load directly
RB = 0 but VA < 

Rout1 is identical to Rout of an emitter-degenerated C-E stage


Gain with VA = and RB  0

Current flowing through rπ

>1 
Will this circuit function?

No dc path for IE
 zero bias current
 Zero gm

Will connecting ‘E’ to Ground help?

 Emitter voltage will always be at ‘0’


 vout = 0

 Emitter requires some bias element


If ; amplifier current will > current through RE;

RE will not affect the gain

  drop across RE must be >> VT


Design a CB stage for AV = 10, Rin = 50. Assume IS = 5×10−16 A,
VA =, β = 100, and VCC = 2.5V.

Select RE = 500 such that RE >>1/gm


Vb = IERE + VBE = 1.16 V

Selecting current through R1 & R2 to be 10IB IR1= 52μA


 R1=25.8k
|C1ω|−1 = (1/gm)/20  C1=71pF  R2=22.3k

900MHz cellphone frequency


Emitter Follower

Voltage gain positive and <1

Acts as a voltage divider


Determine AV. Current source is ideal and VA =

Ideal current source  RE 


 Av = 1

A constant current source at emitter


 VBE = VT ln(IC /IS) is constant

With, Vout =Vin − VBE,


VBE = Vin − Vout

 Vout exactly follows Vin if VBE is constant


Rthev = 1/gm

Thevenin voltage is given by the


open-circuit output voltage
produced byQ1
 CC stage with RE =
 Vout = Vin
Determine the voltage gain of a emitter follower driven by a finite
source impedance of RS Assume VA =.

RThev=

VThev= Vin

From the circuit,


CC stage : Input and Output Impedance

 Input Impedance

Increases RE, to a much larger value,


thereby serving as an efficient “buffer”

Output Impedance

Reduces RS thereby providing higher “driving” capability


A CE stage has a AV = 20, Rout=1k. Determine AV if,
(a) The stage drives an 8 speaker directly.
(b) An emitter follower biased at a current of 5 mA is placed
between the CE stage and the speaker.
Assume β =100, VA=, and CC stage is biased with an ideal
current source.

AV before connecting speaker = gmRC


 20=gm1k  gm=20m
AV after connecting speaker = gm(RC//Rsp)
 AV=20m(1k//8)  AV=0.16

AV after connecting CC stage


= gm(RC//Rin1)
 AV=20m(1k//1.328k)  AV=11.4
CC stage : Input and Output Impedance
Determine the small-signal properties of a CC stage using an
ideal current source but with a finite source impedance RS

ideal current source  RE =,

Also, gmrO >> 1, 

Av approaches unity if RS<<(β + 1)rO


Emitter Follower with Biasing

CC stage can operate with a base voltage near VCC without


driving Q1 into saturation

Followers are commonly biased using RB

RBIB << VRE, thus lowering the sensitivity to β


For the CC stage RB = 10k and RE=1k. Calculate the bias current
and voltages if IS=5×10−16 A, β=100, and VCC=2.5V. What happens if
β drops to 50?

Using VBE≈800mV, in above eq.


IC = 1.545mA
 VBE = VT ln(IC /IS) = 0.748V
 IC = 1.593mA

 IBRB =159mV
ICRE =1.593V
β =50

Using VBE≈800mV, in above eq.


IC = 1.417mA
 VBE = VT ln(IC /IS) = 0.745V
 IC = 1.462mA

 IBRB =292mV
ICRE =1.462V
Twofold change in β leads <10% change in IC
Assuming VA =, compute the voltage gain
Assuming VA =, compute AV and input impedance
Calculate AV, VA =
Determine the input impedance , VA =
Compute AV and Rout, VA < 
Determine AV and I/O impedances. Assume VA = and equal β for
all transistors
The circuit must be designed for maximum AV while maintaining
Q1 in the active mode. If VA = 10V and VBE = 0.8 V, calculate the
required bias current. Assume VCC=2.5V

VC = VCC – ICRC = VBE = 0.8V  IC =

ro = VA/IC gm= IC/VT

AV = gm(ro//RC)
Suppose the bipolar transistor in the circuit exhibits the following
hypothetical characteristic: and no Early effect.

Compute AV for a bias current of 1 mA.

AV = gmRC

gm = dIC/dVBE =
The circuit employs an ideal current source as the load. If the Av=
50 and Rout=10k, determine the bias current of the BJT.

Rout = 10k  ro = 10k

AV = gmro = ICro/VT = 50  IC =

Determine AV, Rin and Rout. Assume VA = .

Rout = r2//1/gm2 1/gm2

AV = -gm1Rout = -gm1[1/gm2]
Rout
Rin = r1
Determine AV, Rin and Rout. Assume VA = .

Rout = R1 + [r2//1/gm2] = R1+1/gm2

AV = -gmRout = -gm1{R1 + 1/gm2}

Rin = r1

Determine AV, Rin and Rout. Assume VA = .

Rout = RC + Rout1 = RC + [r2//1/gm2]


Rout1

AV = -gm1Rout = -gm1[r2//1/gm2] Rout1 = r2//1/gm2

Rin = r1
Determine AV, Rin and Rout. Assume VA = .

Rout = r2//1/gm2

AV = -gmRout = -gm[r2//1/gm2]
Rout
Rin = r1 Rout = r2//1/gm2

Determine AV, Rin and Rout. Assume VA = .

AV = [Vout/Vout1] [Vout1/Vin]
= {-gm[r2//1/gm2]}[1-gm2RC] Vout1
Vout1 Rin = r1 Vout/Vout1 = 1-gm2RC
Rout1 = r2//1/gm2
Rout = RC + [r2//1/gm2]
Design the circuit with AV = 10, Q1 operating at the edge of
saturation. Calculate the bias current and the value of RC if β = 100,
IS = 5×10−16A, and VA =. Calculate Rin

 AV = ICRC/(VT+ICRE) = 10

 ICRC= 10(VT+0.2IC)  (1)


At the edge of saturation; VCE  VCC – IC(RC+RE) = VBE

VBE = 0.8V  ICRC = 1.7 – 0.2IC  (2)

Solve (1) and (2) for IC

From IC solve for VBE=VTln(IC/IS) =

Iterate above steps till values stabilize RC= [10(VT+0.2IC)]/IC


Rin= r + (1+)RE
Determine AV. Assume IS = 7×10−16A, β = 100, and VA = 5 V. (But
for bias calculations, assume VA =).

IB=(VCC-VBE)/[10k+(1+)RE]

If VBE = 0.8V, IB=


 I =IB
C

VBE=VTln(IC/IS) =

Iterate above steps till values stabilize

gm=IC/VT= r=/gm= rO=VA/IC=


AV=91k//0.1k//rO)/[1/gm+(1k//0.1k//rO)]
Circuit is a “Darlington pair.” Assume VA = and the collectors of
Q1 and Q2 are tied to VCC.
(a) If the emitter of Q2 is grounded, determine the impedance seen
at the base of Q1.
(b) If the base of Q1 is grounded, calculate the impedance seen at
the emitter of Q2.
(c) Compute the current gain of the pair, defined as (IC1 + IC2)/IB1.

(a) Rin = r1 + (1+ 1) r1

(b) Rout1 = r1 // 1/gm1

Rout2 = [r2+Rout1]/(1+ 2)

(c) IC1 =  1IB1 IE1 = (1+ 1)IB1

IC2 =  2IB2 =  2IE1 = (1+ 1) 2IB1

(IC1 + IC2)/IB1 =  1+(1+ 1) 2


In the circuit, Q2 serves as a current source for the input device
Q1. (a) Calculate the output impedance of the current source, RCS.
(b) Replace Q2 and RE with the impedance obtained in (a) and
compute the voltage gain and I/O impedances of the circuit.
Design the circuit for maximum AV but with an Rout  500.
Allowing the transistor to experience at most 400mV of base-
collector forward bias, design the stage.

With no early effect, maximum gain


 RC = Rout = 500

VC = VCC - ICRC = VBE – VBC = VBE – 0.4

If VBE = 0.8V, IC =