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Under equilibrium
Since E = −dV/dx,
Dividing both sides by p &
taking the integral,
We have =VT
pp ≈ NA pn ≈ ni2/ND
np ≈ ni2/NA
nn ≈ N D (1.77 × 10−17A)
BJT can modeled as a voltage-dependent current source
Negative sign indicates input & output are out of phase by 180º
To achieve this
emitter is doped much heavily than base
We can write;
Current Density
Where
BJT indeed operates as a voltage controlled current source
Denoting VBE of discrete & integrated circuit BJT as VBEint & VBEdis,
IC=1.69mA
IC = ISexp(VBE/VT) = 1.685mA
Since the current drawn from the collector and flowing into
the emitter depends only on VBE
Since IB=IC/=[ISexp(VBE/VT)]/,
IB = IC/ = 11.53A
IE = IB + IC = 1.165mA
(ii) IC for a given VBE with varying VCE (VCE > VBE)
we get, gm = 0.0385 −1
= 0.0385℧
= 0.038A/V
= 0.038S
gm could be visualized as the slope of IC -VBE characteristic at a given
collector current IC0 and the corresponding base-emitter voltage VBE0
vπ = v1
where
Similarly,
Considering IC varies with VCE,
gm=IC/VT=0.038 -1
rπ=/gm=2.63k
ro=VA/IC = 15 k
BJT has IC = 1mA with VCE = 2V. Determine VBE if VA =∞ and
VA = 20 V. Assume IS = 2×10−16A
β degrades by 10%
= 180mV
VBC = 570mV
The BJT model can be re-constructed as
gm=IC/VT
IX=IS1exp(VBE/VT) VBE=
IY=IS2exp(VBE/VT) =
IB1=IX/ 1 =
IB2=IY/ 2 =
VB=(IB1+IB2)R1+VBE =
In the circuit determine the maximum value of V CC that
places Q1 at the edge of saturation. Assume I S = 3 × 10−16 A.
Collector Voltage VC = Base Voltage VB
VCC=ICRC + VC IC = ISexp(VB/VT)
VCC= RCISexp(VB/VT) + VB
(b) VB =
(a) Determine the signal level sensed by the amplifier if the circuit
has an input impedance of 2k or 500.
(b) Determine the signal level delivered to the speaker if the circuit
has an output impedance of 10 or 2
Signal level sensed by the amplifier V1 = Vm[Rin/(Rin+Rm)]
Vout = Vamp[RL/(RL+Ramp)]
Impedance = VX/IX
Assuming that the transistor operates in the active region,
determine the input impedance.
higher β or
lower IC yield a higher input impedance
Neglecting the Early effect calculate the impedance seen
at the emitter of Q1
Since vπ = 0, gmvπ = 0
Rout = rO
To avoid saturation
For the circuit determine the collector bias current to
avoid. β = 100 and IS = 10−17 A. Verify that Q1 operates in
the active region.
Assuming VBE = 800mV
saturation modes
Because VCC − VBE determines IB,
IC depends on β,
In the previous example, if β increases from 100 to 120,
IC rises to 1.98 mA
and VCE falls to 0.52, driving the transistor to saturation
VBE = 796mV
VX = 906mV
IE = VP/RE=1.06mA
(2) Based on the expected variations of R1, R2, and VBE, choose a
value for VRE ≈ ICRE, say 200 mV
VX VBE+VRE =978mV
IB =5A
I1=VCC/(R1+R2) = 50A
R1+R2 = 50k
VCC−RCIC>VX RC<3k
Redesign the circuit to provide a gm of 1/52. Assume VCC =
2.5V, β=100, and IS=5×10−17A. Determine the maximum value
of RC. Assume VRE= 500mV and I1≥100IB
gm= IC/VT IC=0.5mA
IB =IC/=5A
Assuming VRE= 500mV;
VRE =ICRE RE= 1k
VX VBE+VRE =1.278V
IB =5A
I1=VCC/(R1+R2) = 500A
R1+R2 = 5k
VCC−RCIC>VX RC<2.4k
Reduction in RC translates to a lower voltage gain
Ri Ri1
= 1.545mA
= 0.807V
VY = RBIB+VBE = 0.955 V
VBE=0.791V
VY=0.872V
Design Guidelines
If RC>>RB/β,
we choose
Design the self-biased circuit for gm=1/13 and VCC=1.8V.
Assume IS=5×10−16A and β = 100.
VBE=754mV
RC=475
RB=4.75k
P = ICVCC=1mW IC = 0.556 mA
Input of 2-mV p-p signal gives 107.8-mV p-p output, driving BJT
into heavy saturation
Av = −gm(RC ||rO)
Rin = r
Rout = ro//RC
The circuit is biased with a IC of 1 mA and RC = 1 k. If β = 100 and
VA=10 V, determine the small-signal voltage gain and the I/O
impedances.
CE stage with Early Effect
No external load; RC
= gm/r =
= ro/(ro+RC)
CE Stage With Emitter Degeneration
With β>>1, we can assume gm>>1/rπ
RC = 520
With degeneration = 10
1 + gmRE = 2 RE = 26
Rout = RC = 520
Compute the voltage gain and I/O impedances.
Assume a very large value for C1
RE = 426 = 104
≈ 2.8 k
Determine the voltage gain and I/O impedances. Assume a very
large value for C1 and neglect Early effect.
rO = VA/IC = 10 k
1 + gmRE = 2
We have
Determine the output resistance
CE Stage with Biasing
VC =VCC(8)/[1k+8] = 8mV
Coupling capacitor C2
overcomes this problem
RE = 400
For gain to be unaffected by
degeneration;
IB=IC/ = 10μA;
R1 + R2 = 90 k
Input and Output Impedance
With base grounded,
Early effect neglected,
rπ = β/gm >> 1/gm,
>1
Will this circuit function?
No dc path for IE
zero bias current
Zero gm
Vb = IERE + VBE = 1.16 V
RThev=
VThev= Vin
Input Impedance
Output Impedance
IBRB =159mV
ICRE =1.593V
β =50
IBRB =292mV
ICRE =1.462V
Twofold change in β leads <10% change in IC
Assuming VA =, compute the voltage gain
Assuming VA =, compute AV and input impedance
Calculate AV, VA =
Determine the input impedance , VA =
Compute AV and Rout, VA <
Determine AV and I/O impedances. Assume VA = and equal β for
all transistors
The circuit must be designed for maximum AV while maintaining
Q1 in the active mode. If VA = 10V and VBE = 0.8 V, calculate the
required bias current. Assume VCC=2.5V
AV = gm(ro//RC)
Suppose the bipolar transistor in the circuit exhibits the following
hypothetical characteristic: and no Early effect.
AV = gmRC
gm = dIC/dVBE =
The circuit employs an ideal current source as the load. If the Av=
50 and Rout=10k, determine the bias current of the BJT.
AV = gmro = ICro/VT = 50 IC =
AV = -gm1Rout = -gm1[1/gm2]
Rout
Rin = r1
Determine AV, Rin and Rout. Assume VA = .
Rin = r1
Rin = r1
Determine AV, Rin and Rout. Assume VA = .
Rout = r2//1/gm2
AV = -gmRout = -gm[r2//1/gm2]
Rout
Rin = r1 Rout = r2//1/gm2
AV = [Vout/Vout1] [Vout1/Vin]
= {-gm[r2//1/gm2]}[1-gm2RC] Vout1
Vout1 Rin = r1 Vout/Vout1 = 1-gm2RC
Rout1 = r2//1/gm2
Rout = RC + [r2//1/gm2]
Design the circuit with AV = 10, Q1 operating at the edge of
saturation. Calculate the bias current and the value of RC if β = 100,
IS = 5×10−16A, and VA =. Calculate Rin
AV = ICRC/(VT+ICRE) = 10
IB=(VCC-VBE)/[10k+(1+)RE]
VBE=VTln(IC/IS) =
Rout2 = [r2+Rout1]/(1+ 2)
If VBE = 0.8V, IC =