FABRICATION OF HIGH-K THIN FILMS &

INVESTIGATION OF THEIR PROPERTIES

FOR MOS DEVICES
Under the Guidance of

Prof. P. RAJESH KUMAR,

H.O.D.,
Department of ECE

Presented by:
DASARI MONICA
Organization of this presentation

Literature Introduction
Modelling,
Synthesis
Fabrication
Analysis/Characterization
Applications
Short comings based on the literature
( from each group 1 or 2 short comings)
Objective based on the literature
Introduction of Literature

TiO2 Based Gate Capacitors [1-9],[19],[20],[25]

Other dielectric material Based Gate Capacitors
Mathematical Simulation using TCAD [13-18]
Application oriented literature [5,27],
Review papers[24,27, 28, 30]
Grouping of papers
• RF Sputter
• ALD
• DC Sputter
• E-beam
• Sol-gel Spin Coating Method
Possible Oxide Materials

[5]
? Only few materials: Cheap process cost, abandunt availability, thin film, high-k, good adhesion with base
layer
For a brief idea…. MOS device Operation

Ref:[google, wikipedia]
• Rapid scaling down of the transistor forced
the decrease of the gate dielectric thickness and the
channel
length, which resulted in a drastic increase in leakage
current due to direct tunneling.[1-11]

• High-k gate dielectrics are used to suppress excessive

transistor gate leakage and power consumption.[1, 2, 4]

• TiO2, HfO2, ZrO2, La2O3, Ta2O5, Y2O3, CeO2, AL2O3 and the
composites of Oxides can be used as the High-k Substitute
to SiO2.[2, 4]
Applications in the Literature
• In the field of VLSI/ULSI IC fabrication
Technology[19,20,21]
• DRAM (Memory Chips) device fabrication[5,27]
• Microprocessor Design of the Computers[19,20]
• Mobile and Portable Gadgets[20]
• Gas Sensors, Solar cells [19]
• CMOS DEVICES, MOSFET FABRICATION [21,22,24]

• In all the electronics applications where ever Integrated

Circuits (ICs) are required. The properties of the TiO2 thin
films depend on the deposition techniques as well as on
the deposition conditions. The optimization of preparation
process is important to obtain TiO2 film with appropriate
phase composition [19]
Modelling
• TCAD - modelling Software required for

• Gate capacitor modelling [14,18]

• Performance analysis under varying gate
lengths of a MOS transistor [13,18]
• Oxide Thickness and Substrate Doping
[14,16,17]
• Gate Stack modeling [15]
Experimental Procedure***
• High-k dielectric material coated on P-Silicon or n-Silicon
substrate

• In all the fabrication techniques and Aluminum is coated

on the top layer for contact.
• Metal(p-Silicon) –
Insulator(High-k Dielectric) –
Metal(Aluminium) forms a Capacitor.
Ex: Al/TiO2/p-Si, Al/HfO2/p-Si
• Some process parameters are prefixed and some are
optimized.
• Characterization will be followed to check the results.
• Many iterations will be carries out for better output.
Fabrication

• RF sputtering [2],[6],[8],[10]27
• DC Magnetron Sputtering[1],[3],[4],[8]
• Sol-Gel [1],[6],[7]
• Photolithography [3],[4],[8]
• Furnace [2],[3],[4],[8],[10],[11]
• Spin coater [4],[6],[7]
• Thermal evaporation [1-4],[6],[10]27
• Sonicater [6][7]
• Atomic layer Deposition [11]27
Analysis/Characterization
• Ellipsometer [1],[4],[6],[8]
• C-V analyzer [2],[3],[4],[10]
• XRD [1-4],[6,7],[9-11][19,20]
• AFM [1-3][19,20]
• FESEM [4], [7],[9,10]
• RAMAN SPECTRA [1],[3],[8]
• LCR METER [1],[3]
• UV-VISIBLE SPECTROSCOPY [3],[4],[9]
• STYLUS PROFILO METER [4]
• CONDUCTIVE AFM ( C-AFM) [R7]
• KEITHLEY (4200 SCS) [8],[10]
• FTIR [7],[9]
• TEM [9],[11]
 Substrate k Leakage
Dielectric Substrate bias Working Sputtering Dielectric Annealing current
Ref Material Method Temp voltage Pressure Power Thickness EOT constant Bandgap temp density

DC 3.5 ev
magnetron NOT To
1 TiO2 sputtering 303K -150V 5x10-4pa 200W MENTIONED 6.2 – 19 3.42EV NOT DONE
3.50eV 1.2x10-6
(@6730k)– to
3.55eV 5.9x10-9
(@7730k) A/cm2
DC Decreased Decreased @9730k
magnetron Room 1. To from to 3.43eV 6730k –
3 TiO2 sputtering Temp (-150V) 6x10-2pa 200W 110nm 41 -32 @9730k 9730k

DC
magnetron
sputtering, Room Voltage 39nm &
4 TiO2 Sol-gel Temp not Applied 10-3 mbar 100W 43nm 18 & 73 3.6eV 5500C
1.8x10-6
To 5.4x10-8
A/Cm2
DC
magnetron NOT
8 TiO2 sputtering 303-673K 5x10-4pa - - MENTIONED 19.6 2.37 -

DC
magnetron 1x10-6
sputtering Room Voltage not 60nm 11nm 20.1 A/Cm2
6 TiO2 RF sputtering Temp Applied NA NA 61nm 1.8nm 133.3 NA 9600C
 Voltage not 120nm to
2 TiO2 RF sputtering Room Temp Applied 3x10-3pa 50W-60W 140nm 40-87 7000C
2.2x10-6
A/cm2
to
1.7x10-7
A/Cm2
@6730k

Voltage not
5 TiO2 RF sputtering 303-673K Applied NA NA NA NA 14 - 36 NA NA
5x10-7 A/Cm2

11 TiTaO RF sputtering 400C NA NA NA NA NA 59 NA 3500C

-

Plasma
9 TiO2 Enhanced CVD <4500C - - - 30nm 80 - -

Sol-gel, Spin For 15

10 TiO2, SiO2 coating 600C - Mins NA - 3.45 NA 2000C
8.33x10-6
To 3.7x10-7
A/Cm2
Sol-gel, Spin Rpm :
7 TiO2 coating - - 400rpm NA 36nm 34 NA 6000C
Short coming from the Literature of TiO2
material
• From the above literature it can summarized that
TiO2 films can be formed to give good dielectric
constant (k) through DC Magnetron sputtering at
room temperature and NO substrate bias
voltage.
• The short coming is: Better Dielectric constant Is
observed with lower sputter powers.
• Conclusion : One can try to Optimize the high-k
dielectric with varying sputter powers and Post
deposition annealing temperatures.
[5]
Objective
(Based on the literature)

• To achieve higher dielectric constant (k) while

not sacrificing the EOT (Equivalent Oxide
thickness) under a fairly high bandgap.
• Preparation of the think film in Anatase
crystalline form will boost the required
parameters. Hence the process parameter can
be optimized to get aimed crystallinity of the
film.
•
[27]
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• [27]