Memory

What is the need for memory?

 Storage-for later use
 For archival purposes
 For extraction of information from group of data
 For taking decisions
 Memory
• Tri-State Buffer
• Bus
• Register Files
• Memory
o Scratch Pad Register
o RAM Operation
o Dynamic RAM
o Non-Volatile Memory
• ROM
• EPROM
• EEPROM
 Tri-State Buffer
• In digital electronics three-state, tri-state, or 3-
state logic allows an output port to assume a high
impedance state in addition to the 0 and 1 logic
level, effectively removing the output from the
circuit.

• In active high control, if C=1, Y=X and In active low control, if C=0, when
C=1, Y is isolated from X. Y=X and when C=0, Y is isolated
from X.
 Tri-State Buffer (TSB) - Application
Multiplexer
a) Using Basic Gates b) Using TSB

X1 Z

X0
XOR Gate with Active high Control
Tri-State Buffers
 Advantages of tristate buffer
• Isolates the output from input
• Acts as an electronic amplifier
• Makes connections and data transfer quite flexible
A B
C2
C1 Segment 2

Segment 1
C4
C3

D E
Keep C 2 & C3 off
segment 1 & segment 2 independen t
C 2  1  Data transfer from segment 1 to segment 2
C3  1  Data transfer from segment 2 to segment 1

VLSI ~ 108 elements ~ 10 6 gates

different connection lines exists
TS buffers
connect - reconnect - reconnect differentl y
All by turning ON/OFF TS buffers
 TS Buffer key player in VLSI circuits
 Bus
Set of ‘n’ signal lines (conducting wires) used together to
carry signal corresponding to address or control or data or
program (code) is known as BUS.

Fig (1)General diagram – to show DATA, Address and Control Bus

Address Address
Data Bus (9) Program Bus (13)
Memory Memory
(512B) (8KW)

Data Program Memory

Bus (8) Bus (14)
Fig (2) PIC 16F877A - Program and Data Memory to show DATA, Address and Program Memory Bus
 Register Files
A set of registers arranged in an orderly manner is
called a register file.

Types:
a) Serial – Data is loaded one behind the other-
serially/sequentially and read in the similar
manner

a) Parallel – The register to which the data to be

transferred is directly accessed.
 Serial Register File

Register with address A0 b0 b1 b2 b7

Register with address A1 b0 b1 b2 b7

Register with address A2 b0 b1 b2 b7

b0 b1 b2 b7
Register with address A3
8 SRS arranged side by side
Designated b 0 , b1 ,.b 6 , b 7
Byte - wide
Each SR has 4 stages
Stages assigned addresses A 0 , A1 , A 2 , & A 3

A 0 – referes to byte at A 0 & so on

Byte - wide data loaded at top
Each  of clock shifts data byte by one position
 First In First Out (FIFO) Register file
Data serially shifted IN at top Data serially shifted OUT at bottomIn same order –
delay line for data
FIFO – simplest register file Queue
FIFOfor processing Delay line

Input FIFO Output

Reg Content Content Content Content Content Content

Add. before after after after after after fifth
first first second third fourth clock
clock clock clock clock clock
I/P Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
A0 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
A1 Byte 0 Byte 1 Byte 2 Byte 3
A2 Byte 0 Byte 1 Byte 2
A3 Byte 0 Byte 1
O/P Byte 0
2. Last In First Out (LIFO) Register file

Input /
LIFO
Output

Register file – modified to move data up or down

LIFO – STACK
Important component of a Micro Controller
Data in  to top of stack
Data out  from top of stack
 Memory – Parallel Register File
• A parallel register file is more widely known as a
memory.

• Classified based on – 1. Hardware.

2. Size.
3. Function.
 Scratch Pad Register (Read/Write)
Generally an RS flip-flop is used as basic memory
cell – 1 bit read/write.
4-Byte RAM Register File
M-Byte RAM Register File

Number of registers :M = 2n

Where ‘n’ is number of

address lines.
 RAM – Read operation

Any device using the read data has to wait for at least tp1 ns
before the data can be taken as reliable.
With a delay of tp2 ns data lines are turned off.
 RAM – Write operation

T1- minimum time provided for changes in all lines

T2 – time allowed for data to settle down before the clock signal is asserted
 RAM - Types
• DRAM
- Storage -Gate of a MOS transistor /capacitor
accumulates charge and decides the status of transistor
as on or off.
- Charge leaks; stored information is lost- tens of ms
- To sustain the charge, the charge has to be
replenished and restored at regular intervals
- Done by shifting the charge by one location at
regular intervals; this shifting operation is built into
DRAM
 SRAM and DRAM comparison
• SRAM
• built around RS flip flop
• DRAM
• Built around the MOS transistor and a capacitor
combination
• Occupies less space compared to SRAM
• For the same IC size and price, DRAM capacity is one
order higher than SRAM capacity
• Stored information is lost without replenishment at
regular intervals.
Volatile and Non Volatile memories
• SRAM and DRAM functions only when
energized; once the power is off ,stored data
gets erased
These are VOLATILE memories.
NON VOLATILE memories:
can store data even if the power supply is
switched off.
Example:ROM
 ROM - Types

• PROM

• EPROM

• EEPROM
Example of PROM
 Microcontroller V/S Microprocessor

Harvard Von Neumann

RISC CISC
PIC Microcontroller – 16F877A.
 DATA TRANSFER UNIT
• A set of functional elements linked together to facilitate a
variety of data transfer is called ‘Data Transfer Unit’ (DTU).
1. RE – Read Enable OWE OE
2. WE – Write Enable
3. RCLK – RAM write Clock

Output register
RE
4. RAWE – RAM Address Write Enable RAM file registers

5. RAMACLK – RAM Address Clock RCLK Output

6. WR – Working register Read WE

7. WW – Working register Write

Data bus
RAM address OCLK
8. WCLK - Working register Write Clock decoder

IE
9. OWE – Output Write Enable
10. OE – Output Enable RAM address
register RAMACLK

Input register
11. OCLK – Output CLock Memory
RAWE address
12. IE – Input Enable Input

13. ICLK – Input Clock WR

Working register
WCLK
ICLK

WW
 RAM File Registers

Data Bus (8)

RE
RAM file
registers (128 × 8) RCLK
WE

RAM address
decoder

RAM address
register
RAMACLK
RAWE
Memory Address (7)
 Input Port

Data Bus

IE
Input register
ICLK

Input
 Output Port

Output

OE
Output register
OCLK

OWE
Data Bus
 Working Register

Output

WR
Working register
WCLK

WW
Input
Data Bus
 DTU OPERATION
• The DTU as a whole has 13 control signals.
• Five of these are clock signals used to load data
into the respective registers.
• These can be generated from a single clock signal
as shown below.
WE CLK RAWE WW OWE IE

RCLK RAMACLK WCLK OCLK ICLK

 DTU Operations
Status of control lines
Sl. RAWE RE WE I OWE WW WR Activity
No. E
01 0 0 0 1 0 1 0 Transfer data from input port to
working register
02 1 0 0 0 0 0 0 Write address into RAM address
register (get ready to select an
address location in the register file)
03 0 0 1 0 0 0 1 Transfer data from working register
into the selected RAM location
04 0 0 0 0 1 0 1 Transfer data from working register
to the output port
05 0 1 0 0 0 1 0 Transfer data from selected RAM
location into the working register
06 0 1 0 0 1 0 0 Transfer data from selected RAM
location into the output port
07 0 0 1 1 0 0 0 Transfer data from input port to the
selected RAM location
Enhanced DTU
Enhanced DTU With addition of ALU
 OPCODE AND PROGRAM

• An instruction set, or command set, is the basic set of

commands understood by the microcontroller.
• Instruction set is unique for a microcontroller.
• Instruction consists of a mnemonic – a keyword and
data / address ( In some cases only mnemonic).
- movlw 0x76 – movlw - keyword, 0x76 –data
- movwf 0x24 – movwf - keyword, 0x24 - addr
- Clrw – Only key word
• Each instruction represents a binary sequence which
stands for an operation that can be carried out.
• The bit combination representing an instruction is
called an instruction opcode.
• Whole set of instructions represented by respective
opcodes is called the instruction set of the processor.
• An instruction sequence that can be loaded into the
instruction register one by one and executed to achieve
a definite and well defined objective is called a
program
• Set of opcodes representing all possible operation that
can be carried out by the processor is called a
‘Machine cycle’
 Program Execution Sequence
• Once an instruction sequence (program) is
prepared and loaded into the PM, the EDTU is
ready for operation: The operational sequence
is as follows:
• PC is initialized and points to the location
where the first instruction to be executed is
stored
• The instruction is fetched and loaded into the
instruction register; this constitutes the fetch
cycle/phase of instruction execution
 Program Execution (Contd…)
• The instruction in the instruction register is
decoded by the instruction decoder and
executed; this constitutes the execution phase
of instruction execution.
• PC is incremented. The instruction fetch
operation during fetch cycle and execute
operation during execute cycle are carried out
for the second instruction.
• The PC is again incremented, the third
instruction fetched and executed and so on.
 Program Execution (Contd…)

• The instruction fetch and execute cycles

together is called a ‘Machine Cycle’. Thus
program execution is a sequence of machine
cycles carried out as desired.
• Process continues till the last instruction of the
program.
Processor operation – timing and sequence
 Processor operation – timing and sequence
• The clock has 4 phases – designated Φ1, Φ2, Φ3
and Φ4.
• Four successive clock pulses together
represent an interval in which an instruction
can be fetched or executed. It is called the
‘instruction cycle’.
• As such a machine cycle – fetch and execute
operations together – lasts for 2 instruction
cycles or 8 clock periods.
• Parallel processing takes place – Hence while
executing ith instruction (i+1)th instruction can
be fetched. ( Harvard Architecture )