Computer Organization

Submitted By:
Shaveta Gupta(IT)
3 Fundamental Components of
Computer
 The CPU (ALU, Control Unit, Registers)
 The Memory Subsystem (Stored Data)
 The I/O subsystem (I/O devices)
Address Bus
Data Bus Memory
CPU
Control Bus Subsystem

I/O Device
Subsystem 2
Each of these Components are
connected through Buses.
 BUS - Physically a set of wires. The
components of the Computer are
connected to these buses.
 Address Bus
 Data Bus
 Control Bus

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 Address Bus

 Used to specify the address of the

memory location to access.
 Each I/O devices has a unique address.
(monitor, mouse, cd-rom)
 CPU reads data or instructions from
other locations by specifying the
address of its location.
 CPU always outputs to the address bus
and never reads from it. 4
 Data Bus

 Actual data is transferred via the data

bus.
 When the cpu sends an address to
memory, the memory will send data via
the data bus in return to the cpu.

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 Control Bus

 Collection of individual control signals.

 Whether the cpu will read or write data.
 CPU is accessing memory or an I/O
device
 Memory or I/O is ready to transfer data

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 I/O Bus or Local Bus
 In today’s computers the the I/O
controller will have an extra bus called
the I/O bus.
 The I/O bus will be used to access all
other I/O devices connected to the
system.
 Example: PCI bus

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 Instruction Cycles
 Procedure the CPU goes through to
process an instruction.
 1. Fetch - get instruction
 2. Decode - interperate the instruction
 3. Execute - run the instruction.

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 CPU organization
 CPU controls the Computer
 The CPU will fetch, decode and execute
instructions.
 The CPU has three internal sections:
register section, ALU and Control Unit

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 Register Section
 Includes collection of registers and a
bus.
 Processor’s instruction set architecture
are found in this section.
 Non accessible registers by the
programmer. These are to be used for
registers to latch the address being
accessed and a temp storage register.
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Arithmetic/Logic Unit (ALU)

 Performs most Arithmetic and logical

operations.
 Retrieves and stores its information
with the register section of the CPU.

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 MEMORY ORGANIZATION
• Memory Hierarchy

• Main Memory

• Auxiliary Memory

• Associative Memory

• Cache Memory

• Virtual Memory

• Memory Management Hardware`

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Memory
Main memory consists of a number of
storage locations, each of which is
identified by a unique address
The ability of the CPU to identify each
location is known as its addressability

Each location stores a word i.e. the

number of bits that can be processed by
the CPU in a single operation. Word
length may be typically 16, 24, 32 or as
many as 64 bits.

A large word length improves system

performance, though may be less efficient on
occasions when the full word length is not
used

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 Memory Hierarchy

MEMORY HIERARCHY

Memory Hierarchy is to obtain the highest possible

access speed while minimizing the total cost of the memory system
Auxiliary memory
Magnetic
tapes I/O Main
processor memory
Magnetic
disks

CPU Cache
memory

Register

Cache

Main Memory

Magnetic Disk

Magnetic Tape
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 Memory Subsystem
 2 Types of Memory:
– ROM : Read Only Memory
 Program that is loaded into memory and
cannot be changed also retains its data even
without power.
– RAM : Random Access Memory
 Also called read/write memory. This type of
memory can have a program loaded and then
reloaded. It also loses its data with no power.

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 Different ROM Chips
 Masked ROM :
 ROM that is programmed with data when
fabricated. Data will not change once installed.
Hardwired.
 Programmable ROM (PROM) :
 Capable of being programmed by the user with
a ROM programmer. Not hardwired.
 Erasable PROM (EPROM) :
 Much like the PROM this EPROM can be
programmed and then erased by light.
 EEPROM :
 Another form of EPROM but is reprogammable16
 Different RAM Chips
 Dynamic RAM (DRAM) :
 Leaky capacitors. Caps are charged and slowly
leak until they are refreshed to there original
data locations. Ex. Computer RAM
 Static RAM (SRAM) :
 Much like a register. The contents stay valid
and does not have to be refreshed. SRAM is
faster than DRAM but cost more Ex. Cache
– Each RAM chip has 2^n * m. n address
inputs and m bidirectional data pins 17
The operation of cache memory

1. Cache fetches data from 2. CPU checks to see

next to current addresses in whether the next instruction
main memory it requires is in cache

Cache
Main
Memory CPU
Memory
(SRAM)
(DRAM)

3. If it is, then the

4. If not, the CPU has to
instruction is fetched from
fetch next instruction from
the cache – a very fast
main memory - a much
position
slower process

= Bus connections 18
 Addressing Modes
 Immediate
 Direct
 Indirect
 Register
 Register Indirect
 Displacement (Indexed)
 Stack
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 Immediate Addressing
 Operand is part of instruction
 Operand = address field
 e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
 No memory reference to fetch data
 Fast
 Limited range 20
Immediate Addressing
Diagram
Instruction
Opcode Operand

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 Direct Addressing
 Address field contains address of
operand
 Effective address (EA) = address field
(A)
 e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
 Single memory reference to access data
 No additional calculations to work out
effective address 22
Direct Addressing Diagram
Instruction
Opcode Address A
Memory

Operand

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Direct Addressing Diagram
Instruction
Opcode Address A
Memory

Operand

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 Indirect Addressing (1)
 Memory cell pointed to by address field
contains the address of (pointer to) the
operand
 EA = (A)
– Look in A, find address (A) and look there
for operand
 e.g. ADD (A)
– Add contents of cell pointed to by contents
of A to accumulator 25
 Indirect Addressing (2)
 Large address space
 2n where n = word length
 May be nested, multilevel, cascaded
– e.g. EA = (((A)))
 Draw the diagram yourself
 Multiple memory accesses to find
operand
 Hence slower
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IndirectInstruction
Addressing Diagram
Opcode Address A
Memory

Pointer to operand

Operand

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 Register Addressing (1)
 Operand is held in register named in
address filed
 EA = R
 Limited number of registers
 Very small address field needed
– Shorter instructions
– Faster instruction fetch

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 Register Addressing (2)
 No memory access
 Very fast execution
 Very limited address space
 Multiple registers helps performance
– Requires good assembly programming or
compiler writing
– N.B. C programming
 register int a;
 c.f. Direct addressing 29
Register Addressing Diagram
Instruction
Opcode Register Address R
Registers

Operand

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 Register Indirect Addressing

 C.f. indirect addressing

 EA = (R)
 Operand is in memory cell pointed to by
contents of register R
 Large address space (2n)
 One fewer memory access than indirect
addressing
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 Register Indirect Addressing Diagram

Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

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 Displacement Addressing
 EA = A + (R)
 Address field hold two values
– A = base value
– R = register that holds displacement
– or vice versa

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 Displacement Addressing Diagram

Instruction
Opcode Register R Address A
Memory

Registers

Pointer to Operand + Operand

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 Relative Addressing
 A version of displacement addressing
 R = Program counter, PC
 EA = A + (PC)
 i.e. get operand from A cells from
current location pointed to by PC
 c.f locality of reference & cache usage

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 Base-Register Addressing
 A holds displacement
 R holds pointer to base address
 R may be explicit or implicit
 e.g. segment registers in 80x86

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 Indexed Addressing
 A = base
 R = displacement
 EA = A + (R)
 Good for accessing arrays
– EA = A + (R)
– R++

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 Stack Addressing
 Operand is (implicitly) on top of stack
 e.g.
– ADD Pop top two items from stack
and add

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Input-Output Organization

 11-1 Peripheral Devices

– I/O Subsystem
 Provides an efficient mode of communication
between the central system and the outside
environment
– Peripheral (or I/O Device)
 Input or Output devices attached to the
computer
 11-2 Input-Output Interface
 1) A conversion of signal values may be
required
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  2) A synchronization mechanism may be needed
– The data transfer rate of peripherals is usually slower than the
transfer rate of the CPU
 3) Data codes and formats in peripherals differ from the
word format in the CPU and Memory
 4) The operating modes of peripherals are different from
each other
– Each peripherals must be controlled so as not to disturb the
operation of other peripherals connected to the CPU
– Interface
 Special hardware components between the CPU and
peripherals
 Supervise and Synchronize all input and output transfers
I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard 40
and Magnetic Magnetic
Printer
display disk tape
terminal
– Transfer
– Synchronous Data Transfer
 All data transfers occur
simultaneously during the
occurrence of a clock pulse
 Registers in the interface
share a common clock with
CPU registers
– Asynchronous Data Transfer
 Internal timing in each unit
(CPU and Interface) is
independent
 Each unit uses its own private
clock for internal registers

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 Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

(a) Block diagram (a) Block diagram

Data  Valid data

Data
 Valid data

Strobe  Strobe 
(b) Timing diagram (b) Timing diagram

Fig. 11-3 Source- Fig. 11-4 Destination-

initiated strobe initiated strobe

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 Data bus Data bus

Source Data valid Destination Source Data valid Destination

unit unit unit unit
Data accepted Ready for data

(a) Block diagram

(a) Block diagram

Data
 Valid data

Ready for data


Data valid 
– Handshake : Agreement betwee
Data valid

Data accepted
 Data bus
 Valid data

(b) Timing diagram

(b) Timing diagram
Source unit Destination unit
Source unit Destination unit
Place data on bus
Enable data valid. Accept data from bus Ready to accept
Enable data accepted data.
Place data on bus Enable ready for data
Enable data valid.

Disable data valid

Invalidate data on bus Disable data accepted
Ready to accept data
(initial state)
(c) Sequence of events
Accept data from bus
Disable data valid Disable reday for data
Invalidate data on bus
(initial state)
(c) Sequence of events

Fig. 11-5 Source-initiated handshake

Fig. 11-6 Destination-initiated h

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 11-4 Modes of Transfer Read status register

– Data transfer to and from peripherals Check flag bit

 1) Programmed I/O = 0
Flag

 2) Interrupt-initiated I/O = 1

Read data register

 3) Direct Memory Access (DMA) Transfer data to memory

 4) I/O Processor (IOP)

Operation no
complete ?

Interrupt-initiated I/O yes

Continue

1) Non-vectored : fixed branch

with
program

address
 2) Vectored : interrupt source
supplies the branch address
(interrupt vector)

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– Polling
 Identify the highest-priority source by software
means
– One common branch address is used for all
interrupts
– Program polls the interrupt sources in sequence
– The highest-priority source is tested first
 Polling priority interrupt
– If there are many interrupt sources, the time
required to poll them can exceed the time available
to service the I/O device
– 따라서 Hardware priority interrupt
– Daisy-Chaining :
Processor data bus
VAD 1 VAD 2 VAD 3

“1” “1” “0”

Device 1 Device 2 Device 3
To next
PI PO PI PO PI PO
Device

Interrupt request
INT
CPU
Interrupt acknowledge
INTACK

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 VAD

INTACK Priority in
PI Enable
Vector address

INT Priority out

RF PO
Interrupt S Q
request
from device One stage of the daisy-chain priority
PI RF PO Enable
arrangement : Fig. Delay
11-13
R
 00 0
1
0
0
0
0
Open-collector
 1 0 1 0
inverter  1 1 1 1
Interrupt request to CPU 

 No interrupt request
 Invalid : interrupt request, but no acknowledge
 No interrupt request : Pass to other device
(other device requested interrupt )
 Interrupt request

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 Direct Memory Access (DMA)
– DMA
 DMA controller takes over the buses to manage
the transfer directly between the I/O device
and memory

DBUS Address bus

BR BR High-impedance
Bus request ABUS Data bus
DMA (disable)
CPU when BG is
Controller
RD Read enabled
BG BG
Bus grant WR Write
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– Transfer Modes
 1) Burst transfer : Address bus

 2) Cycle stealing transfer

– DMA Controller ( Intel 8237 DMAC ) Data bus Address bus
Data bus buffers
 DMA Initialization Process buffers

– 1) Set Address register :

bus
 memory address for read/write Address register
DMA select CS

Internal
– 2) Set Word count register : Register select RS
 the number of words to transfer Read RD Word count register

– 3) Set transfer mode : Write WR

Control
Control register
4) DMA transfer start : Bus request BR logic

Bus grant BG
– 5) EOT (End of Transfer) : DMA request
Interrupt Interrupt
to I/O device
DMA Acknowledge

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– DMA Transfer (I/O to Memory)
 1) I/O Device sends a DMA request
 2) DMAC activates the BR line
3) CPU responds with BG line
Interrupt
 BG CPU
Random access
memory (RAM)

4) DMAC sends a DMA acknowledge

BR

RD WR Address Data RD WR Address Data

to the I/O device Read control

Write control

 5) I/O device puts a word in the data Data bus

Address bus

bus (for memory write)

 6) DMAC write a data to the address Address
select

specified by Address register RD WR Address Data

7) Decrement Word count register

DMA acknowledge
DS
 RS Direct memory I/O
access (DAM) Peripheral

 8) Word count BR
BG
controller
DMA request
device

9) Word count register

Interrupt


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 Input-Output Processor (IOP)
– IOP
 Communicate directly with all I/O devices
 Fetch and execute its own instruction
– IOP instructions are specifically designed to facilitate
I/O transfer
– DMAC must be set up entirely by the CPU
 Designed to handle the details of I/O
processing

Central Processing
unit (CPU)
Memory bus

Peripheral devices
Memory unit PD PD PD PD

Input-output
processor (IOP) I/O bus

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– CPU - IOP Communication
 Memory units acts as a message center :
– each processor leaves information for the other

CPU operations IOP operations

Send instruction
Transfer status word
to test IOP path
to memory location

If status OK. , send

start I/O instruction Access memory for
to IOP IOP program

Conduct I/O transfer

CPU continues with
using DMA ; prepare
another program
status report

I/O transfer completed

interrupt CPU

Request IOP status

Transfer status word

to memory location

Check status word

for correct transfer

Continue

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 Input/output Devices
 Input/output devices are required for
users to communicate with the
computer.
 In simple terms, input devices bring
information INTO the computer and
output devices bring information OUT of
a computer system. These input/output
devices are also known as peripherals.
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 Input Devices are:

 Keyboard
 Mouse
 Joystick
 Scanner
 Light Pen
 Touch Screen

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 Output devices are:

 Printers
 Plotters
 Monitor
 LCD

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Intel 8086/8088 Microprocessors
 Intel 8086 and 8088 Microprocessors are
the basis of all IBM-PC compatible
computers
(8086 introduced in 1978, first IBM-PC released in 1981)

 All Intel, AMD and other advanced

microprocessors are based on and are
compatible with the original 8086/8
 At Power Up and Reset time, Pentiums,
Athlons etc all look like 8086 processors
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Intel 8086/8088 Microprocessors
 Intel 8086 is a 16b microprocessor:
– 16b data registers, 16b ALU
 Width of external data bus:
– 8086: 16b
– 8088: 8b
 Width of external address bus: 16b+4b=20b
 Some techniques to optimise the CPU
performance when it’s executing programs
 Segment: Offset memory model
 Little-Endian Data Format 56
 8086/8088
 Original IBM PC used 8088 microprocessor
 8088 is similar to the 8086, but it has an
external 8b data bus & only 4B-deep queue
– For cost reduction reasons
 We can consider 8086 and 8088 together
 PC clones often used 8086 for better
performance
 8-bit bus reduces performance, but meant
cheaper computers
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 8086/8088 Functional Units

Bus Interface
Unit(BIU)
Execution Unit
Fetches Opcodes,
(EU)
Reads Operands,
Writes Data

8086/8088 MPU
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 8086/8088
 8086/8088 consists of two internal units
– The execution unit (EU) - executes the
instructions
– The bus interface unit (BIU) - fetches
instructions, reads operands and writes results
 The 8086 has a 6B prefetch queue
 The 8088 has a 4B prefetch queue

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8086/8088 Internal Organisation
EU BIU

Address Bus 20 bits

AH AL SUMMATION

BH BL
Data Bus

CH CL
CS
DH DL
DS
SP
SS
BP
ES
DI
IO
BI
Internal Bus
Communications Control
Registers
8088
Bus

Temporary
Registers

Instruction Queue

ALU
EU
Control
1 2 3 4

Flags

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 BIU Elements
 Instruction Queue: the next instructions or data can be
fetched from memory while the processor is executing
the current instruction
– The memory interface is slower than the processor execution
time so this speeds up overall performance
 Segment Registers:
– CS, DS, SS and ES are 16b registers
– Used with the 16b Base registers to generate the 20b address
– Allow the 8086/8088 to address 1MB of memory
– Changed under program control to point to different segments
as a program executes
 Instruction Pointer (IP) contains the Offset Address of
the next instruction, the distance in bytes from the
address given by the current CS register 61
8086/8088 20-bit Addresses

CS

16-bit Segnment Base Address 0000

IP

16-bit Offset Address

20-bit Physical Address

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 BIU Elements
 Instruction Queue: the next instructions or data can be
fetched from memory while the processor is executing
the current instruction
– The memory interface is slower than the processor execution
time so this speeds up overall performance
 Segment Registers:
– CS, DS, SS and ES are 16b registers
– Used with the 16b Base registers to generate the 20b address
– Allow the 8086/8088 to address 1MB of memory
– Changed under program control to point to different segments
as a program executes
 Instruction Pointer (IP) contains the Offset Address of
the next instruction, the distance in bytes from the
address given by the current CS register 63
 MAXIMUM MINIMUM
MODE MODE

GND 1 40 Vcc
AD14 AD15
AD13 A16,S3
AD12 A17,S4
AD11 A18,S5
AD10 A19,S6
AD9 /BHE,S7
AD8 MN,/MX
AD7 /RD
AD6 /RQ,/GT0 HOLD
AD5
8086 /RQ,/GT1 HLDA
AD4 /LOCK /WR
AD3 /S2 IO/M
AD2 /S1 DT/R
AD1 /S0 /DEN
AD0 QS0 ALE
NMI QS1 /INTA
INTR /TEST
CLK READY
GND 20 21 RESET

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 8086/8088 Summary
 First Generation (introduced June 1978)
 One of the first 16b processors on the
market
 16b internal registers
 16/8b external data bus
 20b address bus (1MB addressable)
 Used in 1st generation IBM PCs (1981)
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 Thanks

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