BASIC VLSI DESIGN

MD.MASOOD AHMAD
ASSISTANT PROFESSOR
ECE DEPARTMENT
 UNIT I

A Review of Microelectronics and an

introduction to MOS technology
 Objectives of UNIT I
• Basic MOS transistor action
• Overview of fabrication processes
• nMOS fabrication
• CMOS fabrication
• P-well process
• N-well process
• The twin tub process

8/6/2019 UNIT I 3
 Introduction to IC Technology
• Moore’s law
• 1965
• Components density would double for every
year
• 1975
• Components density would double for 18
months
• 1995 Moore,s law hold good and even today.
8/6/2019 UNIT I 4
 Cramming more components onto
integrated circuit

8/6/2019 UNIT I 5
 Moore’s prediction

• By 1975 the number of

components per integrated
circuit for minimum cost will be
65,000 transistors

8/6/2019 UNIT I 6
 IC Technology
Technology No of Typical
transistors products
10-100 Logic gates,FF
SSI
MSI 100-1000 Counters,mux,decodersand
adders

LSI 1000-20,000 MP,RAM ,ROM

VLSI 20,000-1,000,000 DSP,RISC,32 bit , 64 bit MP

ULSI 1,000,000-10,000,000 Special processors

8/6/2019 UNIT I 7
 MOSFET BASICS

FET’s classification
 Types of Field Effect Transistors
(The Classification)

n-Channel JFET
» JFET
FET p-Channel JFET

MOSFET (IGFET)

Enhancement Depletion
MOSFET MOSFET

n-Channel p-Channel n-Channel p-Channel

EMOSFET EMOSFET DMOSFET DMOSFET

8/6/2019 UNIT I 9
 N channel Depletion MOSFET

8/6/2019 UNIT I 10
N channel Enhancement type MOSFET

8/6/2019 UNIT I 11
N channel Enhancement type MOSFET

8/6/2019 UNIT I 12
 MOSFET Symbols

8/6/2019 UNIT I 13
N channel Enhancement type MOSFET

8/6/2019 UNIT I 14
 Current –voltage relationship

8/6/2019 UNIT I 15
 Current –voltage relationship

8/6/2019 UNIT I 16
 Drain characteristics

8/6/2019 UNIT I 17
 MOS FET terminal identification
• NMOSFET
• A terminal with high potential is drain.
• A terminal with low potential is source.
• PMOSFET
• A terminal with high potential is source.
• A terminal with low potential is drain.

8/6/2019 UNIT I 18
N-MOS Fabrication Process

Si-substrate

Fig. (1) Pure Si single crystal

------------------------
-------------------------
--------------------------
-------------------------

Fig. (2) P-type impurity is lightly

doped
 N-MOS Fabrication Process

Thick SiO2
(1 µm)
------------------------
-------------------------
--------------------------
-------------------------

Fig. (3) SiO2 Deposited over si surface

Photoresist
Thick SiO2
(1 µm)
------------------------
-------------------------
--------------------------
-------------------------
Fig. (4) Photoresist is deposited
over SiO2 layer
 N-MOS Fabrication Process

UV Light

Mask-1

Photoresist
Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
Mask-1 is used to expose the SiO2
where S, D and G is to be formed.

Fig. (5) Photoresist layer is

exposed to UV Light through a
mask
 N-MOS Fabrication Process

Polymerised
Photoresist

-------------------------------
----------------------------------
Thick SiO2
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (1 µm)
----------------------------------

Fig. (6) Developer removes unpolymerised photoresist. It

will cause no effect on Si surface
 N-MOS Fabrication Process

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------

Fig. (7) Etching [HF acid is used] will remove SiO2 layer
which is in direct contact with etching solution
 N-MOS Fabrication Process

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------

Fig. (7) unpolymerised photoresist is also etched away

[using H2SO4]
 N-MOS Fabrication Process

Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------

Fig. (8) A thin layer of SiO2 grown over the entire chip surface
 N-MOS Fabrication Process

Polysilicon layer
(1 – 2 µm)

-------------------------------
---------------------------------- Thin SiO2
Thick SiO2 (0.1 µm)
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (1 µm)
----------------------------------

Fig. (9) A thin layer of polysilicon is grown over the entire chip
surface to form GATE
 N-MOS Fabrication Process

Photoresist

Polysilicon
layer

------------------------------- Thin SiO2

---------------------------------- (0.1 µm)
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2
---------------------------------- (1 µm)

Fig. (10) A layer of photoresist is grown over polysilicon layer

 N-MOS Fabrication Process

UV Light

Mask-2

-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
Mask-2 is used to deposit
Polysilicon to form gate.
Fig. (11) Photoresist is exposed to UV Light
 N-MOS Fabrication Process

Polysilicon
Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------

Fig. (12) Etching will remove that portion of Thin SiO2 which is
not exposed to UV light
 N-MOS Fabrication Process

Polysilicon used as GATE

(1 – 2 µm)

Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------

Fig. (13) Polymerised photoresist is also stripped away

 N-MOS Fabrication Process

GATE

SOURCE DRAIN

Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------
----------------------------------

Fig. (14) n+ Doping to form SOURCE and DRAIN

 N-MOS Fabrication ProcessStep -
Metallization

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2
(1 µm)
Thick SiO2
---------------------------------- (1 µm)

Fig. (15) A thick layer of SiO2 (1 µm) is again grown.

 N-MOS Fabrication ProcessStep -
Metallization

UV Light

Mask-3

Mask-3 is used to make contact cuts for S, D and G.

Photoresist

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2
(1 µm)
Thick SiO2
---------------------------------- (1 µm)

Fig. (16) Photoresist is grown over thick SiO2. Selected areas of the poly GATE and SOURCE and
DRAIN are exposed where contact cuts are to be made
 N-MOS Fabrication ProcessStep -
Metallization

Mask-3

Photoresist

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2
(1 µm)
Thick SiO2
---------------------------------- (1 µm)

Fig. (17) The region of photoresist which is not exposed by UV light will become soft. This
unpolymerised photoresist and SiO2 below it are etched away.
 N-MOS Fabrication ProcessStep -
Metallization

Mask-3

Photoresist

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2
(1 µm)
Thick SiO2
---------------------------------- (1 µm)

Fig. (18) The contact cuts are formed for S, D and G (hardened photoresist is stripped away).
 N-MOS Fabrication ProcessStep -
Metallization

Metal (1µm)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2
(1 µm)
Thick SiO2
---------------------------------- (1 µm)

Fig. (19) Metal (aluminium) is deposited over the surface of whole chip (1 µm thickness).
 N-MOS Fabrication ProcessStep -
Metallization

Photoresist

Metal (1µm)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2
(1 µm)
Thick SiO2
---------------------------------- (1 µm)

Fig. (20) Photoresist is deposited over the metal.

 N-MOS Fabrication ProcessStep -
Metallization

UV Light

Mask-4

Photoresist
Metal (1µm)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2
(1 µm)
Thick SiO2
---------------------------------- (1 µm)

Mask-4 is used to deposit metal in contact cuts of S, D and G.

Fig. (21) UV Light is passed through Mask-4 (with a aim of removing all metal other than metal in
contact-cuts).
 N-MOS Fabrication ProcessStep -
Metallization

Mask-4

Photoresist
Metal (1µm)

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------ Thick SiO2
(1 µm)
Thick SiO2
---------------------------------- (1 µm)

Fig. (22) Photoresist and metal which is not exposed to UV light are etched away.
 N-MOS Fabrication ProcessStep -
Metallization

SOURCE DRAIN
GATE

- - - - - - - - - - - - -- -- -- - - - -- -- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -- -- - - - - - - - - - - - -
-- - - - - - - - - - - - - n+
- - - - - - - -n+ ------------
----------------------------------

Fig. (23) Final n-MOS Transistor

 CMOS Fabrication
• CMOS transistors are fabricated on silicon
wafer
• Lithography process similar to printing press
• On each step, different materials are
deposited or etched
• Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process

8/6/2019 UNIT I 41
 Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

8/6/2019 UNIT I 42
 Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
• Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

8/6/2019 UNIT I 43
 Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line
A

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

8/6/2019 UNIT I 44
 Detailed Mask Views
• Six masks n well

– n-well
– Polysilicon Polysilicon

– n+ diffusion n+ Diffusion

– p+ diffusion p+ Diffusion

– Contact Contact

– Metal
Metal

8/6/2019 UNIT I 45
 Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate
 Oxidation
• Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate
 Photoresist
• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate
 Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist

Photoresist
SiO2

p substrate

UNIT I
8/6/2019 Slide 49
 Etch
• Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been
exposed

Photoresist
SiO2

p substrate

UNIT I
8/6/2019 Slide 50
 Strip Photoresist
• Strip off remaining photoresist
– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

SiO2

p substrate

UNIT I
8/6/2019 Slide 51
 n-well
• n-well is formed with diffusion or ion
implantation
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
• Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si

SiO2

n well

UNIT I
8/6/2019 Slide 52
 Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of
steps

n well
p substrate

UNIT I
8/6/2019 Slide 53
 Polysilicon
• Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

UNIT I
8/6/2019 Slide 54
 Polysilicon Patterning
• Use same lithography process to pattern
polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

UNIT I
8/6/2019 Slide 55
 Self-Aligned Process
• Use oxide and masking to expose where n+
dopants should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-
well contact

n well
p substrate

UNIT I
8/6/2019 Slide 56
 N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned
gates because it doesn’t melt during later
processing

n+ Diffusion

n well
p substrate

UNIT I
8/6/2019 Slide 57
 N-diffusion cont.
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+

n well
p substrate

UNIT I
8/6/2019 Slide 58
 N-diffusion cont.
• Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

UNIT I
8/6/2019 Slide 59
 P-Diffusion
• Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate

UNIT I
8/6/2019 Slide 60
 Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

UNIT I
8/6/2019 Slide 61
 Metalization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

UNIT I
8/6/2019 Slide 62
 Example of n-well process

• There are number of p-well

and n-well fabrication
processes steps
• One example of n-well
process is BERKELEY n-well
process.
8/6/2019 UNIT I 63
 Thermal aspects of processing
• CMOS p-well diffusion processes
takes place at 1100 to 1250 C
• NMOS fabrication having no such
requirement

8/6/2019 UNIT I 64
 Comparison between CMOS and
bipolar technologies
CMOS Technology
Low static power dissipation
High input impedence
Scalable threshold voltage
High noise margin
High packing density
High delay sensitivity to load
Low out put derive current
Low gain
Bidirectional capability
A near ideal switch
8/6/2019
Bipolar technology
High power dissipation
Low input impedence
Not possible
Low voltage swing logic
Low packing density
Low delay sensitivity to load
High output drive current
High gain
Essentially unidirectional
Not a ideal switch
UNIT I 65
 Bi CMOS Technology

• Bipolar technology plus

CMOS technology

8/6/2019 UNIT I 66
Bicmos fabrication in an n well process
• Form N-well
• Form buried N plus layer(BCCD)*
• Delineate active areas
• Channel stop
• Form deep N plus collector*
• Threshold voltage adjustment
• Delineate poly/gate areas
• Form n plus active areas
• Form p plus active areas
• Form P plus base for bipolar*
• Define contacts
• Delineate the metal areas
8/6/2019 UNIT I 67
 Some aspects of bipolar and CMOS
devices
• CMOS for logic
• BICMOS for I/O and driver circuits

8/6/2019 UNIT I 68
 Production of E-Beam masks
• The masks are produced by standard optical
techniques
• E-Beam machine is used for E-Beam mask
preparation
• E-Beam mask preparation steps
• The starting material consists of chrome-plated
glass which are coated with an E- Beam sensitive
resist
• The E-Beam machine is loaded with the mask
description data
8/6/2019 UNIT I 69
 Production of E-Beam masks
• Plates are loaded into the E-Beam machine
Where they are exposed with the patterns
specified by the customer’s mask data
• After expose to the E-Beam,the plates are
introduced into a developer to bring out the
patterns left by the E-Beam in the resist coating
• The cycle is followed by a bake cycle and a plasma
de-summing ,which removes the resist residue
• The chrome is then etched and the plate is
stripped of the remaining E-Beam resist
8/6/2019 UNIT I 70
 Production of E-Beam masks
• The advantages of E-Beam mask are
• 1)Tighter layer to layer registration
• 2)smaller feature size
• There are two approaches to the design of E-
Beam machines
• Raster scanning
• Vector scanning

8/6/2019 UNIT I 71