Overview of INTEL family Processor

Intel 4004
Year of introduction : 1971
4 bit microprocessor with 2300 transistors
A Programmable controller on chip
4 KB main memory
Used PMOS technology
Rate of execution 50 KIPs
Clock speed was 500 KHz to 740 KHz
Instruction set include 45 Instructions
 Intel 4040

Introduced in 1974 by Intel

Upgraded version of 4004
Clock speed was 740 kHz (same as the 4004
microprocessor)
3,000 transistors integrated
Interrupt features were available
Programmable memory size: 8 KB
640 bytes of data memory
24-pin DIP
 Intel 8008
Year Of Introduction : 1972
First 8 bit microprocessor
Instruction set includes 48 instructions
Addressable memory 16 KB (main memory)
Clock rate 500 kHz with Execution speed 0.05 MIPS
3,500 transistors
 Intel 8080
Year of introduction : 1973
Up graded version of 8008
8-bit microprocessor
64 KB main memory
It was faster than 8008 and can handle 50k
instructions per second.
Used NMOS technology.
Considered as the first General purpose
microprocessor.
 Intel 8085
Year of Introduction : 1976
Used only one +5V power supply rather than 3
Power supply needed in earlier 8080.
8 bit microprocessor
40 Pin DIP
Clock speed 3 MHz with execution speed 0.37 MIPs
Number of Transistors used 6,500
 Intel 8086
Released in 1978
16 bit microprocessor.
Data bus width: 16 bits
Address bus: 20 bits
Addressable memory 1 Megabyte
Include Execution Unit (EU), and Bus Interface Unit (BIU)
Clock rates: 5 MHz, 0.33 MIPS
8 MHz, 0.66 MIPS
10 MHz, 0.75 MIPS
The memory is divided into odd and even banks.
It accesses both banks concurrently to read 16 bits of data in one
clock cycle
29,000 transistors used
Used segment registers to access more than 64 KB of data at
once
 Intel 8088
Released in 1979
8088 was a 16 bit microprocessor and contained 29000
transistors.
Clock rates:
4.77 MHz with execution speed 0.33 MIPS
8 MHz, 0.66 MIPS
External data bus width: 8 bits,
Address bus: 20 bits
Addressable memory 1 Megabyte
Identical to 8086 except for its 8-bit external bus
Identical Execution Unit (EU), and Bus Interface Unit (BIU)
Used in IBM PC and PC-XT and compatibles
Later renamed the iAPX 88
 Intel 80186
16 bit Microprocessor
Introduced 1982
Clock rates
6 MHz, > 1 MIPS Execution rate
55,000 transistors
Included two timers, DMA (Direct Memory Access)
controller, and an interrupt controller on the chip in addition
to the processor
Added a few Op-codes to the 8086 design, otherwise
identical instruction set to 8086 and 8088
Address calculation and shift operations are faster than 8086
Later renamed to iAPX 186
 Intel 80286

• Year of Introduction : 1982

• High Performance - 16 bit microprocessor with memory
management & protection.
• Addressable memory 16 MB(main memory)
• Clock rates: 6 MHz with execution rate 0.9 MIPS
8 MHz, 10 MHz with rate of execution 1.5 MIPS
12.5 MHz, 2.66 MIPS
•16 MHz, 20 MHz and 25 MHz available.
• Introduced Virtual memory concept
•Widely used in IBM PCs
Cont..

Data bus width: 16 bits,

Address bus: 24 bits
Included memory protection hardware to support
multitasking operating systems with per-process address
space.
134,000 transistors used
Added protected-mode features to 8086 with essentially the
same instruction set
Widely used in IBM PC-AT
 Intel 80386
Launched in Year : 1986
Intel's First Practical and advanced 32 bit
Microprocessor.
32 bit Address and Data Bus
Also known as i386 or 386
Max CPU Clock rate : 12 MHz to 40 MHz.
Address 4 GB Memory
Concept of Paging was introduced
Instruction set was upward compatible
 Intel 80486
Launched in 1989
32 Bit microprocessor
4GB main memory
Execute up to 40 million instructions per second.
8 K byte Cache on the package.
By the use of Pipelining , Instruction get executed in 1 clock
rather than 2 clocks used in 386.
Clock rates: 25 MHz, Execution rate : 20 MIPS
33 MHz, Execution rate : 27 MIPS
Bus width: 32 bits
1.2 million transistors
Addressable memory 4 GB
Cont….

Virtual memory 64 TB
Level 1 cache of 8 KB on chip
Math coprocessor on chip.
50 X performance of the 8088
Officially named Intel486 DX
 Pentium
Bus width: 64 bits
Introduced in1993
•System bus clock rate 60 or 66 MHz
•Address bus: 32 bits
•Addressable memory 4 GB
•Virtual Memory 64 TB
• Superscalar architecture
•Used in desktops
•8 KB of instruction cache
•8 KB of data cache
•3.1 million transistors
• 273 pin PGA Package
•Package dimensions 2.16″ × 2.16″
•Variants
•60 MHz, 100 MIPS
•66 MHz, 112 MIPS
 Other Intel Processors

Pentium Pro
Pentium II
Pentium III
Pentium IV
Intel Atom
Intel Celeron
Intel Xeon
Intel Pentium Dual Core
Intel Core 2 series
Intel Core i3
Intel Core i5
Intel Core i7
 Real Mode and Protected Mode

•Beginning with 80286, the advanced Intel processors

contain the ability to operate in two different modes of
operation.

•Real Mode

•Protected Mode

•In Real Mode, the advanced processors including Pentium

simply operate like very fast 8086 microprocessor with the
associated 1MB memory limit.
•Real Mode operations is automatically selected upon
power up.

•In protected mode, full 4GB of memory is available to the

processor. Some special priviledged instructions, support
of multitasking, virtual memory addressing, memory
management and protection, control over the internal data
and cache etc. are available.

•The Windows OS runs in protected mode to take

advantage of these improvements.
•The earlier slide showed block diagram of Pentium
processor architecture.

•The Pentium processor is a complex machine with many

interlocking blocks.

•At the heart of two processor are 2 integer pipelines, the U

pipeline and the V pipeline. These pipelines are responsible
for executing instructions.

•A floating point unit is included on the chip to execute

complex mathematical instructions.
•During execution, the U and V pipes are capable of
executing 2 integer instructions at the same time, under
special conditions or one floating point instruction.

•The Pentium communicates with the outside world via

32bit address bus and 64bit data bus.

•The bus unit is capable of performing burst reads and

writes of 32 byte to memory, and through bus cycle
pipelining allows 2 bus cycles to be in progress
simultaneously.

•8 KB instruction cache is used to provide quick access to

frequently used instructions.
•When an instruction is not found in the instruction cache, it
is read from the RAM through external data bus and a copy
placed into the instruction cache for future references.

•The branch target buffer and prefetch buffer work together

with the instruction cache to fetch instructions as fast as
possible.

•The prefetch buffer maintain a copy of the next 32 bytes of

prefetched instruction code and can be loaded from the
cache in single clock circle.

•The Pentium uses technique called Branch Prediction to

maintain a steady flow of instructions into the pipelines.
• To support Branch Prediction, the branch target Buffer
maintains a copy of instructions in different part of the
program located at an address called the branch target
address.

• So, just in case the code from the target address is

needed, the branch target buffer maintains a copy of it and
feeds it to the instruction cache.

•A separate 8 KB data cache stores a copy of the most

frequently accessed memory data.
• The data and Instruction caches may both be enabled /
disabled with hardware or software. Both also employ the
use of a Translation Lookaside Buffer (TLB), which
converts logical address into physical address when virtual
memory is employed.

•The Floating Point Unit (FPU) of the Pentium maintains a

set of floating point registers and provide 80 bit precision
when performing high speed mathematical operations.

•The floating point unit uses hardware in the U and V

pipelines to perform the initial work during a floating point
instruction ( such as fetching a 64 bit operand), and then
uses its own pipeline to complete the operation
 Flags in EFLAG register

C (Carry) : Carry holds the Carry after addition or borrow

after subtraction. This flag is SET ( switched to Logic 1)
automatically when the carry is generated by the earlier
instruction execution.

P ( Parity) : The logic level of this flag automatically becomes 0

when the result of earlier Instruction execution has odd parity
and logic 1 for even parity. Parity is count of logic ones in a
number. If count of logic ones is even then it said to be even
parity number otherwise it is odd parity number.
A (auxiliary carry): The auxiliary carry holds the carry
(half carry) after addition or the borrow after subtraction between
bit positions 3 and 4 of the result. This flag bit is tested by the
DAA and DAS instructions to adjust the value of AL after BCD
addition or subtraction.
Z (zero) :The zero flag shows that the result of an arithmetic
or logical operation is zero. The flag is set when result is zero
otherwise it remain reset (logic 0).

S (sign) :The sign flag holds the arithmetic sign of the result
after execution of arithmetic or logic instruction.
The sign flag is set(logic 1) if the result of earlier instruction
execution is negative and resets (logic 0) when the sign is
positive.
T (trap): The trap flag enables trapping through an on-chip
debugging feature (A program is debugged to find an error or bug)
When set, causes an interrupt after the execution of each instruction.
This is used for debugging of a program. If T flag is logic 0, the
trapping(debugging) feature is disabled.

I (Interrupt enable flag): When set, the processor will recognize

external interrupts. The Interrupt flag controls the operation of
INTR(Interrupt Request) input pin. If I=1, the INTR pin is
enabled. If I=0,it is disabled. The state of I flag bit is controlled
by the STI(Set I Flag) and CLI(Clear I Flag) instructions.

.
D (Direction flag): Determines whether string processing
instructions increment or decrement the 16-bit registers SI and
DI (for 16-bit operations). If D=1, the registers are
automatically decremented. If D=0, they are incremented. The
D flag is set with STD(Set Direction Flag) and clear with
CLD(Clear Direction) Instructions.

O (Overflow flag): Overflows occurs when sign numbers are

added or subtracted. An overflow indicates that the result has
exceeded the capacity of the machines. For eg. If 7FH(+127) is
added using 8 bit addition to 01H(+1), the result is 80H(-128).
This result represents an overflow condition indicated by
overflow flag for signed addition. For unsigned operations, the
overflow flag is ignored.
IOPL (I/O privilege level): IOPL is used in protected mode
operation to select privilege level for I/O devices. If the current
privilege level is higher than IOPL, I/O executes without
hindrance. If IOPL is lower than the current privilege level, an
interrupt occurs causing execution to suspend. When set, causes
the processor to generate an exception on all accesses to I/O
devices during protected-mode operation.

NT (Nested Task): The Nested Task Flag indicates that the

current task is nested within another task in protected mode
operation. This flag is set when the task is nested by software.

RF (Resume flag): The Resume Flag is used with debugging to

control the resumption of execution after the next instruction.
VM (Virtual Mode): The VM flag bit selects virtual mode
operation in protected mode system. Virtual mode system
allows multiple DOS memory partitions that are 1MB in
length to co-exist in the memory system. Essentially this
allows the system program to execute multiple DOS programs.

AC (Alignment check): Activates if a word or double word is

addressed on a non-word or non-double word boundary.

VIF (Virtual Interrupt Flag): The VIF is copy of interrupt

flag bit available to the Pentium 4 microprocessor.

VIP (Virtual Interrupt Pending): VIP provides information

about virtual mode interrupt for the Pentium microprocessor.
This is used in multitasking environments to provide the
Operating System with virtual interrupt flags and Interrupt
Pending Information.
ID (Identification flag ):The ID flag indicates that the
Pentium microprocessor support the CPUID instruction. The
CPUID instruction provides the system with information about
the pentium microprocessor such as its version number and
manufacturer, vendor, family, and model.
 Real mode Memory addressing
• The 80286 and above Microprocessors operate either in
the real or Protected mode.

• Only 8086 and 8088 operate exclusively in the real mode.

• Real mode operation allows the Microprocessor to

address only the first 1MB of memory space even if it is
the Pentium4 Microprocessor.

• First 1MB memory is called either the real memory or

conventional memory system.
Cont…

Real mode operation allows application software written for

the 8086/8088, which contains only 1 MB of memory, to
function in 80286 and above Microprocessors with out
changing the software.
 Segments and Offsets
• A combination of Segment address and Offset address
access a memory location in the Real mode.

• The Real mode memory address (Physical address)

consists of segment address plus offset address.

• The segment address (Base address) located within one of

the segment registers, defines the beginning address of any
64 KB memory segment.

• The offset address selects any location within the 64 KB

memory segment.
• Segments in the real mode always have a length of 64 K
bytes.
 Segment Registers
Generates Physical address with the help of other register.
There are six segment registers which functions differently in
Real Mode and in Protected Mode.
CS (code segment): The Code segment is a section of code
memory that holds the code(programs) used by microprocessors.
The code segment register defines the starting address of the
section of the memory holding code. In real mode operation, it
defines the start of 64KB code section of memory.

DS (data segment): The data segment is a section of memory

that contains most data used by a program. Data are accessed in
the data segment by an offset address or the contents of other
registers that hold the offset address. The code segment length is
limited to 64KB.
• ES (extra segment): ES is an additional data signal that is
used by some of the string instructions to hold destination
data.
• SS (stack segment): The stack segment defines the area
of memory used for stack. The stack’s entry point is
determined by the stack segment and stack segment
register. The BP register also addresses data within the
stack segment.
• FS & GS (F and G segment): The FS and GS segments
are supplemental segment registers available in pentium
microprocessor to allow 2 additional memory segments
for access by program.
Default 16 bit Segment and offset address Combination
Segment Offset Purpose
CS IP Instruction Address
SS SP or BP Stack Address
DS BX or DI or SI Data Address
ES DI for String Instruction Destination
Instructions Address
 Interrupt
An Interrupt is an event that causes the processor
to stop its current program execution and perform
a specific task to serve the interrupt.

Two types of interrupts:

Hardware interrupt
Software interrupt
Interrupt Processing
Interrupt Vector Table
 What Happens When An Interrupt Occurs?

• Push flags register onto the stack

• Clear interrupt enable and trap flags

∗ This disables further interrupts
∗ Use sti to enable interrupts

• Push CS and IP registers onto the stack

• Load CS with the 16-bit data at memory address

interrupt-type ∗ 4 + 2

• Load IP with the 16-bit data at memory address

interrupt-type ∗ 4
 Returning From An ISR
• As in procedures, the last instruction in an ISR
should be iret

• The actions taken on iret are:

∗ pop the 16-bit value on top of the stack into IP register
∗ pop the 16-bit value on top of the stack into CS register
∗ pop the 16-bit value on top of the stack into the flags
Register

• As in procedures, make sure that your ISR does

not leave any data on the stack
∗ Match your push and pop operations within the ISR
Interrupt Processing in Real Mode

• Uses an interrupt vector table that stores pointers

to the associated interrupt handlers.
∗ This table is located at base address zero.

• Each entry in this table consists of a CS:IP pointer

to the associated ISRs

∗ Each entry or vector requires four bytes:

» Two bytes for specifying CS
» Two bytes for the offset

• Up to 256 interrupts are supported (0 to 255).