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Channel Coding

NCU-EE VLSI/DSP Lab.


Freshman Training Course

Speaker : 林承鴻
Advisor: 蔡宗漢 博士

National Central University


Department of Electrical Engineering 2003/07/07 1
VLSI/DSP Lab.
Outline
 Overview of Channel coding
– Digital Communication System
– Types of Error Control
– Types of Channel Coding
 Turbo Codes
– Introduction
– System model
– Log-MAP vs SOVA
– Simulation
– SW – Memory Architectures
 Conclusions
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 2
Digital Communication System
JPEG, RS code, QPSK, QAM,
MPEG, etc. Turbo code, BPSK, etc.
Information Source rb Channel rc
Modulator
Source Encoder Encoder

rs

Channel

Source Channel Demodu-


Data Sink
Decoder Decoder lator
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 3
Channel Coding
 Channel coding refers to the class of signal transformation
designed to improve communication performance by
enabling the transmitted signals to better withstand the
effects of various channel impairments.
 Channel coding can be partitioned into two areas,
waveform (or signal design) coding and structured
sequences (or structured redundancy.)
 Waveform coding deals with transforming waveforms into
“better waveforms,” to make the detection process less
subject to errors.
 Structured sequence deals with transforming data
sequences into “better sequences,” having structured
redundancy.
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 4
Types of Error Control
 Before we discuss the detail of structured redundancy, let
us describe the two basic ways such redundancy is used for
controlling errors.
– Error detection and retransmission, utilizes parity bits

(redundant bits added to data) to detect that an error has


been made and requires two-way link for dialogue
between the transmitter and receiver.
– Forward error correction (FEC), requires a one way

link only, since in this case the parity bit are designed
for both the detection and correction of errors.

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 5
Why Use Error-Correction Coding
 Trade-off:
– Error Performance verse Bandwidth

– Power verse Bandwidth

– Data Rate verse Bandwidth

– Capacity verse Bandwidth

– Coded verse Uncoded Performance

 Coding Gains
– For a given bit-error probabilities, coding gain is

defined as the reduction in Eb/N0 that can be realized


through the use ofEcode. E
G (dB ) = ( b
)u (dB ) − ( b
) c (dB )
N0 N0
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 6
Types of Channel Coding
 Block codes
– Extended Golay code
– Hamming code
– BCH code
 Convolutional codes
– Recursive or Nonrecursive
– Systematic or Nonsystematic
 Reed-Solomon Codes
 Interleaving and Concatenated Codes
 Turbo Codes
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 7
Block Codes
(6,3) Binary Block Code
 (n,k) Block Codes
Messages Code words
– message :
k-tuple u=(u1,u2,…,uk) (0 0 0) (0 0 0 0 0 0)
– code word : (1 0 0) (1 1 0 1 0 0)
n-tuple v=(v1,v2,…,vn) (0 1 0) (0 1 1 0 1 0)
– code rate : (1 1 0) (1 0 1 1 1 0)
R=k/n
(0 0 1) (1 1 1 0 0 1)
(1 0 1) (0 0 1 1 0 1)
(0 1 1) (1 0 0 0 1 1)
(1 1 1) (0 1 0 1 1 1)
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 8
Convolustional Codes
 (n,k,m) Convolutional Codes
– message :
k-tuple u=(u1,u2,…,uk) (2,1,2) Convolutional Code
– code word : u2
n-tuple v=(v1,v2,…,vn)
– code rate : s2 s1
Input bit
R=k/n
b D D
– memory order :
m u1
– Constraint length :
K=m+1
– Generator polynomials :
g1(x)= 1+x+x2; g2(x)=1+x2
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 9
Outline
 Overview of Channel coding
– Digital Communication System
– Types of Error Control
– Types of Channel Coding
 Turbo Codes
– Introduction
– System model
– Log-MAP vs SOVA
– Simulation
– SW – Memory Architectures
 Conclusions
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 10
Turbo Codes
 Shannon’s channel coding theorem guarantees the existence of codes
that can achieve arbitrary small probability of error if the data
transmission rate is smaller than the channel capacity.

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 11
Applications
 Turbo code is currently adopted as the channel coding
schemes in many next-generation communication systems
– WCDMA, CDMA2000
– CCSDS in space communications
– Baseband Signal compensation in Fiber transmission systems
Application Area Applied System

Space Data Consultative Committee for Space Data


Transmission Systems (CCSDS)

(a) 3rd Generation Partnership Project


(3GPP)
Cellular mobile
(b) CDMA2000

Satellite
Communication INMARSAT
Network

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 12
Specifications in WCDMA
Type of TrCH Coding scheme Coding rate

BCH 1/2

Convolutional coding
PCH

RACH

1/3, 1/2
CPCH, DCH, DSCH, FACH
Turbo coding 1/3

No coding

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 13
Specification in CDMA2000
Channel Type Forward Error Code Rate
Correction code

Access Channel Convolutional 1/3

Enhanced Access Channel Convolutional 1/4

Reverse Common Control Channel Convolutional 1/4

Reverse Dedicated Control Channel Convolutional 1/4

Reverse Fundamental Channel Convolutional 1/2, 1/3, 1/4

Reverse Supplemental Code Channel Convolutional or 1/2, 1/3


Turbo code 1/2, 1/3, 1/4

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 14
Turbo Code v.s. Convolutional
Code
Convolutional Code Turbo Code
 Non-recursive  Recursive
 Non-systematic  Systematic

 Without Interleaver  Parallel structure

 Use Interleaver
NSC
RSC

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 15
Design Flow

Design
Design Place
Place&&Route
Route
Architecture
Architecture
Design
Design
Specification
Specification
Behavior
BehaviorLevel
Level Dracula
Dracula
Simulation
Simulation DRC,
DRC,LVS,
LVS,LPE
LPE
High
HighLevel
Level
Simulation
Simulation
Synthesis
Synthesis&&Gate
Gate Post-Layout
Post-Layout
Simulation
Simulation Simulation
Simulation

Tap out
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 16
System Model
dk Xk
MemorylessNoise
n
Y1k x

Parallel-to-serial
BPSK +
RSC1 Puncturing
Modulator
Y2 k
r
Interleaver

RSC1

Denterlever

Λ1e Λ2 e
ro Interlever
r1
Serial-to-parallel

Decoder1 Decoder2
BPSK
r2
Demodulator
~ Λ2
Interlever ro

Hard
National Central University
Denterlever
Decision
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 dk 17
Log-MAP vs SOVA
G=[75], Unpunctured(1/3),

framesize=1024,

Iteration Iteration=8.
SOVA
increment..

Iteration

increment..

Log_MAP

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 18
The SOVA algorithm

Input
symbols

Store Trace back

sign
Delay Line
weight

ML path

National Central University


Competitor path
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 19
Log-MAP Algorithms
γ k ( S ) = log γ k ( S ) =
2
(
1 e s s
Lin ( xk ) xk + Lc yks xks + Lc ykp xkp )
M s −1

∑ ∑ (e rk i ( Sk−1 ,S )+α k−1 ( Sk−1 ) ) α k ( S ) = MAX (rk i ( S k −1 , S ) + α k −1 ( S k −1 ))


*
α k ( S ) = log S k −1 ,i
S k −1 = 0 i∈0 ,1

M s −1
β k ( S ) = log ∑ ∑ (
S k +1 = 0 i∈0 ,1
e rk +1i ( S , S k +1 ) + β k +1 ( S k )
) β k ( S ) = MAX * (rk +1i ( S , S k +1 ) + β k +1 ( S k ))
S k +1 ,i

M s −1
LLRk ( S ) = log ∑ (eα
S k =0
k ( S k ) + rk +1 1( S , S k +1 ) + β k +1 ( S k )
) LLRk ( S ) = MAX * (α k ( S k ) + rk +11( S , S k +1 ) + β k +1 ( S k ))
Sk
M s −1
− MAX * (α k ( S k ) + rk +1 0( S , S k +1 ) + β k +1 ( S k ))
− log ∑ (e
S k =0
α k ( S k ) + rk +1 0 ( S , S k +1 ) + β k +1 ( S k )
) Sk

MAX * ( x, y ) = ln(e x + e y ) = MAX ( x, y ) + ln(1 + e − ( x − y ) )


|x-y| 0~0.25 0.25~0.5 0.5~0.75 0.75~1 1~1.25 1.25~1.5 1.5~2 >2

ln(1+e-|x-y| ) 0.75 0.5 0.5 0.5 0.25 0.25 0.25 0

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 20
Log-MAP Algorithms

t0 t t
α k −1 (0) 1 γ k (0,0) α k (20) γ k +1 (0,0)
t3 β k +1 ( 0) t4 t5
S0 S0
γ k (1,0) β k (0)

α k −1 (1) γ k +1 (0,2)
S1 S1
β k +1 (2)
S2 S2

S3 S3

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 21
Sliding Window – Memory Issue
 The extrinsic and APP
value are made with a
delay, which is equal
to received sequence
length.
 But the decoder
decisions length can be
reduced to about six
times the encoder
memory because of
reliable decoding
decision.

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 22
Simulation Results (1/3)

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 23
Simulation Results (2/3)
Iteration87653241

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 24
Simulation Results (3/3)

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 25
SW - Memory Architectures
 Advantage:
1 Less memory size. 2. Might be Lower latency.
 Disadvantage:
1.Read-modify-write access required for the memory.
2.Address is hard to be controlled.
RAMA RAM3 RAM2 RAM1

MUX MUX MUX MUX MUX


ACS

ACS

ACS
MUX

MUX
α

β
ACS u ACS c
π k (u; O ) π k (c; O )
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 26
Timing Diagram

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 27
Position VS Time

A
B0 DO

B1
G

Decodeoutput withoutLIFO
National Central University Decodeoutput withLIFO
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 28
ACS Unit
*Add-compare-select(ACS)Unit:

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 29
Forward / Backward Processor
TrellisStates:
S0 S0
ForwardProcessor(A)/BackwardProcessor(B)BlockDiagram:

S1 S1

S2 S2

S3 S3

BlockDiagrambasedon TrellisStates:

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 30
Novel Turbo Code – Iteration
Issues
 In high-quality channel environments, a large of decoding
iterations are not required to obtain the target BER, and it
is possible to terminate the process after a few numbers of
decoding iterations. L (d ) e2 k
Denterlever
Denterlever
xk + La 2 ( d k ) xk + La 2 ( d k )
La1 ( d k )
xk
+
+
− −
+
∑ SISO
SISO ∑ SISO
SISO ∑
Interlever
y1k + (MAP1)
Interlever
(MAP2)
(MAP1) (MAP2)
xk + Le1 (d k )
y2 k Decoder
Decoder
Decoder
Decoder

ThresholdDetection
ThresholdDetection

Hard
Hard Denterlever
L1 ( d k ) Denterlever L2 ( d k )
Decision
Decision
dk
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 31
Outline
 Overview of Channel coding
– Digital Communication System
– Types of Error Control
– Types of Channel Coding
 Turbo Codes
– Introduction
– System model
– Log-MAP vs SOVA
– Simulation
– SW – Memory Architectures
 Conclusions
National Central University
Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 32
Conclusions
 We discuss some fundamentals of channel coding.
 We discuss some basic implementation issues for
turbo codes.
 This study can be exploited in development of
high performance receiver with different
constraints of cost and throughput.
 The novel turbo decoder can practically have
lower iteration with the adaptive SNR channel
estimation.

National Central University


Department of Electrical Engineering
VLSI/DSP Lab. 2003/07/07 33