DESIGN OF SENSE AMPLIFIER FOR COUPLING

SUPPRESSION BY USING 25-nm

TECHNOLOGY
Under the esteemed Guidance of
Supervisor Name : Dr.N.SANGEETHA PRIYA ,M.E,ph.D
Designation : Associate Professor
Department of ECE, RCEE

Batch No.:A-14
Project Area: VLSI
A.Krishna Saranya 15ME1A0401
A.YaswanthKumar 15ME1A0404
Ch.Teja 16ME5A0405
G.Srujanidevi 15ME1A0443

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 Overview of the Presentation
• Abstract
• Introduction
• Objective of the project
• Scope of the project
• Literature Survey
• Problem Definition(Existing, Limitations)
• Proposed model
Block diagram
Circuit diagram
Schematic diagram
Software Modules
Methodology
Working Procedure
Simulation Results
Comparative Results
• Applications&Advantages
• Conclusion
• Future Scope
• References

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 ABSTRACT

• The CMOS channel length and the pitch of the device gets
compressed continuously.

• Coupling effect interferes with the action of Sense Amplifier (SA)

and also a coupling suppressed SA.

• Signals classified & suppressed by different turn on currents.

• Monte Carlo simulation is the proposed simulation for this work.

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 INTRODUCTION

• Benefiting from the development of semiconductor fabrication

technology, many more devices can be integrated on the same area of die.
• In exchange, devices have to suffer from more serious coupling effects
due to the smaller pitch.
• The reduction in the thickness of the gate oxide also strengthens the
coupling effect from MOSFET gate. These will bring more challenges to
memory circuit design, especially for SRAM, which is a critical memory
block for the SOC.
• Sense amplifier (SA) is a basic part of SRAM and is widely used in
SRAM products. Its basic function is to sense the small differential
voltage so as to reduce dynamic power and access time.
• It is highly susceptible to differential noises and offset. Many
researchers have studied the improvement.
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 OBJECTIVE OF THE PROJECT

• To design a new architecture for the improvement of CMOS

device.

• To design Sense Amplifier along with coupling effect for a CMOS

device and memory elements.

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 Scope of the Research
 To reduce the effect of coupling signal in the circuit by using
coupling suppression

 To reduce the area , power, time delay compared with the existing
one

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 LITERATURE SURVEY
S TYPE OF TITLE OF PAPER YEAR OF INFERENCE
NO: JOURNAL PUBLICATION

1 IEEE R. Singh and N. Bhat, 2004 The key to low power

“An offset compensation operation in the SRAM is to
technique for latch type reduce the signal swings on
sense amplifiers in high” the high capacitance bit
lines .The offset in sense
amplifier is due to transistor
mismatch in the supposedly
2 IEEE B.Wicht,T.Nirschl and 2004 with a high-impedance
D.schmitt-landsiedel differential input stage is
“Yield and speed presented. It investigates the
optimization af a latch impact of supply voltage,
type voltage sense input DC level, transistor
amplifier”. sizing, and temperature on
the input offset voltage.

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3 IEEE J. S. Shah, D. Nairn, and M.
Sachdev
“An energy-efficient offset
cancelling sense amplifier”
4 IEEE A. K. Gundu, W. Singh, and S. M.
Divi,
“A proposed low-offset sense
amplifier for SRAM applications,”
5 IEEE Anh-Tuan Do, Zhi-Hui Kong, and
Kiat-Seng Yeo .
Criterion to Evaluate Input-Offset
Voltage of a Latch-Type Sense
Amplifier .
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2013 To increase the overall
packing density, the smaller
transistors exhibit higher
degrees of process variation
and mismatch, leading to
larger offset voltages.
2015 Sram’s become extremely
To process variations
especially as the supply
voltage is reduced .it also
sensing small delay with low
power supply
2010 Several works in the literature
have been dedicated to
investigating the offset
behavior of the cross-coupled
inverters . Most of them only
deal with the threshold
voltage mismatch,
8
 PROBLEM DEFINITION

• There is only a basic function available to sense the small difference

in the voltage so as to reduce the dynamic power and access time.
• This is not convenient enough to reduce the differential noise and
offset time.
• There is a analytical model for SA in which the offset of SA is
studied but the coupling effect is not discussed earlier.
• To reduce the offset time circuit is designed but its doesn’t support
to the timing delay.
• The counter balance of SA has been considered and scientific model
has been fabricated, the coupling impact isn’t referenced obviously.

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 LIMITATIONS

• Large area occupancy

• Time delay is high
• High power consumption
• Noise immunity is low

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 PROPOSED MODEL

• A new high speed and low offset circuit has been given out, but the
extra device matching issue is not emphasized.

• The research focuses on improving initial differential voltage rather

than the SA circuit, which will be the focus of this paper.

• SA’s small signal sensing feature is vulnerable to block operation.

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 BLOCK DIAGRAM
Positive signal

Bit
Line Bit
signal line
bar
PPMOS Inverter Inverter PMOS
Network 1 2 Network

Enable
signal
Inverter
Enable NMOS Network

Negative
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 CIRCUIT DIAGRAM

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 SCHEMATIC DIAGRAM

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 METHODOLOGY

 Tanner EDA (16.01V) is used as a software tool to design the

circuit.

 Windows OS is a system software.

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 SOFTWARE COMPONENTS

Tanner EDA (16.01V)

 Tanner tool is a spice computer analysis programmed for analog

integrated circuits.
 Tanner consists of 4 engine machines:
• S-EDIT (Schematic edit)
• T-EDIT (Simulation edit)
• W-EDIT(Waveforms edit)

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 WORKING PROCEDURE
S-EDIT:-
 Part 1: Setup your Directory Structure & download Libraries
 Part 2: Start a New Design & Setup Libraries
• a) Start S-Edit:
 start – All Programs – Tanner EDA – Tanner Tools v16.01 – S-Edit
v16.01
• b) Start a New Design:
Utilizing the draw down menus, make another outline:
➢ File – New - New Design
• c) Create a new Cell:
A "cell" is an outline component. A cell can contain different
perspectives, for example, schematics and images. Cells can be
instantiated in different cells.
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 WORKING PROCEDURE

• d) Enter the symbol libraries:

To begin with, you have to incorporate a library which contains the
images for all fundamental circuit components, for example, resistors,
NMOS, capacitors, and so on… The libraries for all the essential
images are in the Tanner_Libraries.zip document you downloaded and
unfastened.
• e) Setup the SPICE Models for the Generic_0.25 kit
 Part 3: Enter the Schematic to simulate the IV behavior of an NMOS
Transistor
 Part 4: Setup the Parameters that will be used during the DC sweep
analysis
 Part 5: Setup the SPICE DC Sweep Analysis

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 WORKING PROCEDURE

 Part 6: Simulate the Design

• a) First, check you design using the pull down menus:
➢ Tools – Design Checks (any warnings or errors will be shown at the
bottom)
• b) Simulate your design:
o Clock on the Green Arrow to start the simulator:
The T-Spice window will appear. If everything is OK, the waveform
viewer will also appear.

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 Windows os:
 Microsoft Windows is an operating system for computers which
is made by Microsoft, a company from the United States.

 Microsoft has made several advancements and changes that have

made it is a easier operating system.

 Because of the large amount of Microsoft windows users there is

a much larger selection of available software programs, utilities,
and games for windows.

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 SIMULATION RESULTS

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 RESULTS(SCREEN SHORTS)

EXISTING SYSTEM PROPOSED SYSTEM

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 RESULTS( SCREEN SHORTS)

EXISTING SYSTEM PROPOSED SYSTEM

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 APPLICATIONS & ADVANTAGES

Advantages:

• Area is reduced compare to the existed one.

• Time delay is low .
• Low power consumption.
• Noise immunity is high.

Applications:

• To design memory circuits like SRAM and DRAM

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 CONCLUSION

• The coupling effect of the latch-type decouple voltage SA is

introduced. The coupling effects are serious and could not be
omitted when the process scales down.

• A new design is presented for reducing the harmful coupling. It can

be seen that the robustness can be improved by the new designs
against the harmful coupling with little cost of area and power.

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 FUTURE SCOPE

• Under different voltage and temperature, the new design can offer
improvement steadily. It can be expected that, when entering 16 nm
or a smaller size era, the new design can play a more efficient role
for an even smaller pitch

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 REFERENCES

• B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed

optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-
State Circuits, vol. 39, no. 7, pp. 1148–1158, Jul. 2004.
• A.-T. Do, Z.-H. Kong, and K.-S. Yeo, “Criterion to evaluate input-
offset voltage of a latch-type sense amplifier,” IEEE Trans. Circuits
Syst., vol. 57, no. 1, pp. 83–92, Jan. 2010.
• A. K. Gundu, W. Singh, and S. M. Divi, “A proposed low-offset
sense amplifier for SRAM applications,” in Proc. 2nd Int. Conf.
Signal Process. Integr. Netw. (SPIN), 2015, pp. 965–967.
• B. S. Amrutur and M. A. Horowitz, “A replica technique for
wordline and sense control in low-power SRAM’s,” IEEE J. Solid-
State Circuits, vol. 33, no. 8, pp. 1208–1219, Aug. 1998.

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 THANK YOU

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