CHAPTER 5

CMOS Operations & Fabrication

 Introduction

• So far, we have treated transistors as ideal switches

• An ON transistor passes a finite amount of current
• Depends on terminal voltages
• Derive current-voltage (I-V) relationships
• Transistor gate, source, drain all have capacitance
• I = C (DV/Dt) -> Dt = (C/I) DV
• Capacitance and current determine speed
 MOS Capacitor

• Gate and body form MOS capacitor

• Operating modes polysilicon gate
Vg < 0
• Accumulation +
silicon dioxide insulator
p-type body
-
• Depletion
• Inversion (a)

0 < Vg < Vt
depletion region
+
-

(b)

Vg > Vt
inversion region
+
- depletion region

(c)
 Terminal Voltages
Vg
• Mode of operation depends on Vg, Vd, Vs + +
Vgs Vgd
• Vgs = Vg – Vs - -
• Vgd = Vg – Vd Vs Vd
- +
• Vds = Vd – Vs = Vgs - Vgd Vds

• Source and drain are symmetric diffusion terminals

• By convention, source is terminal at lower voltage
• Hence Vds  0
• nMOS body is grounded. First assume source is 0 too.
• Three regions of operation
• Cutoff
• Linear
• Saturation
n Channel CMOS Operation
 n Channel Cutoff Mode

Vgs=0 Vgd
g
s d
n+ n+
p-type body

• The source and drain have free electrons

• The body has free holes but no free electrons
• The junction between the body and the source or drain are reverse-biased, so almost zero current
flows, Ids ≈ 0
 nMOS Cutoff Mode cont.
pn junction:
reverse bias

iD=0
for vGS<Vt0

Schematic

When vGS=0 then iD=0 until vGS>Vt0 (Vt0 –threshold voltage)

 nMOS Linear Mode
Vgs>Vt Vgd=Vgs Vgs>Vt Vgs>Vgd>Vt

g g Ids
s d s d

n+ n+ n+ n+
p-type body p-type body

Vds=0 0<Vds<Vgs-Vt
• A.k.a. resistive, nonsaturated, or unsaturated region
• If Vgd=Vgs, then Vds=Vgs-Vgd=0 and there is no electrical field tending to push current from drain to
source
• If Vgs>Vgd>Vt, then 0<Vds<Vgs-Vt and there is a small positive potential Vds is applied to the drain ,
current Ids flows through the channel from drain to source
• The current increases with both the drain and gate voltage
 nMOS Linear Mode cont.
For vDS<vGS-Vt0 and vGS>Vt0 the NMOS is operating in the linear region

Resistor like characteristic

(R between S & D,
Used as voltage controlled R)

For small vDS, iD is proportional

to the excess voltage vGS-Vt0
nMOS Linear Mode cont.


i D  K 2v GS  Vt 0 v DS  v DS
2

W  KP
K  
L  2
Device parameter KP for
NMOSFET is 50 mA/V2
 nMOS Saturation Mode
Vgs>Vt Vgd<Vt

g Ids
s d

n+ n+
p-type body
Vds>Vgs-Vt

• The Vds becomes sufficiently large that Vgd<Vt, the channel is no longer inverted near the drain and
becomes pinched off
• However, conduction is still brought about by the drift of electrons under the influence of the positive
drain voltage
• As electrons reach the end of the channel, they are injected into the depletion region near the drain
and accelerated toward the drain
• The current Ids is controlled by the gate voltage and ceases to be influenced by the drain
 nMOS Saturation Mode cont.
Operation in the Saturation Region (vDS is increased)

Tapering
of the
channel
- increments
of iD are
smaller
when
vDS is
larger When vGD=Vt0 then the channel
thickness is 0 and

i D  K vGS  Vt 0 
2
 nMOS Transistor Summary

In summary, the NMOS transistor has three modes of operations

o If Vgs<Vt, the transistor is cutoff and no current flows
o If Vgs>Vt and Vds is small, the transistor acts as a linear resistor in which the
current flow is proportional to Vds
o If Vgs>Vt and Vds is large, the transistor acts as a current source in which the
current flow becomes independent of Vds
The PMOS transistor operates in just the opposite fashion
 Ideal I-V Characteristics of MOS

 In linear and saturation regions, the gate attracts carriers to form a channel
 The carriers drift from source to drain at a rate proportional to the electric field
between these regions
 MOS structure looks like parallel plate capacitor while operating in inversion
 Gate–oxide–channel
Vg

N+ N+
 Nonideal I-V Characteristics of MOS

 Nonideal I-V effects

 Velocity saturation, mobility degradation, channel length modulation, subthreshold conduction,
body effect, etc.
 The saturation current increases less than quadratically with increasing Vgs. This is caused by two effects:
 Velocity saturation
 Mobility degradation
 Velocity saturation
 At high lateral field strengths (Vds/L), carrier velocity ceases to increase linearly with field strength
 Result in lower Ids than expected at high Vds
 Mobility degradation
 At high vertical field strengths (Vgs/tox), the carriers scatter more often
 Also lead to less current than expected at high Vgs
 n Channel I-V Summary

• Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2
 Example

An nMOS has W=160 mm, L=2 mm, KP= 50 mA/V2 and Vto=2 V.

Plot the drain current characteristic vs drain to source voltage

 
for vGS=3 V.
i D  K 2v GS  Vt 0 v DS  v DS
2

 W  KP
i D  K vGS  Vt 0  K  
2
L 2
 Example
Characteristic

Channel length i D  Kv DS
2

modulation
id depends on vDS in
saturation region
(approx: iD =const in
saturation region)
p Channel CMOS Operation
 P Channel Basic Operation
It is constructed by interchanging the n and p regions of n-
channel MOSFET.

Symbol
Characteristic

How does p-channel

MOSFET operate?
-voltage polarities
-iD current
-schematic
 CMOS Fabrication

• CMOS transistors are fabricated on silicon wafer

• Lithography process similar to printing press
• On each step, different materials are deposited or etched
• Easiest to understand by viewing both top and cross-section of wafer
in a simplified manufacturing process
 Inverter Cross-section

• Typically use p-type substrate for nMOS transistors

• Requires n-well for body of pMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

 Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor connection (used
for Schottky Diode)
• Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

 Inverter Mask Set

• Transistors and wires are defined by masks

• Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap
 Detailed Mask Views

• Six masks n well

• n-well
Polysilicon

• Polysilicon
n+ Diffusion

• n+ diffusion
p+ Diffusion

• p+ diffusion Contact

• Contact

• Metal
Metal
 Fabrication Steps

• Start with blank wafer

• Build inverter from the bottom up
• First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer
• Strip off SiO2

p substrate
 Step 1: Oxidation

• Grow SiO2 on top of Si wafer

• 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate
 Step 2: Photoresist

• Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light

Photoresist
SiO2

p substrate
 Step 3: Lithography

• Expose photoresist through n-well mask

• Strip off exposed photoresist

Photoresist
SiO2

p substrate
 Step 4: Etch

• Etch oxide with hydrofluoric acid (HF)

• Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate
 Step 5: Strip Photoresist

• Strip off remaining photoresist

• Use mixture of acids called piranha etch
• Necessary so resist doesn’t melt in next step

SiO2

p substrate
 Step 6: n-well

• n-well is formed with diffusion or ion implantation

• Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si
SiO2

n well
 Step 7: Strip Oxide

• Strip off the remaining oxide using HF

• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

n well
p substrate
 Step 8: Polysilicon

• Deposit very thin layer of gate oxide

• < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate
 Step 9: Polysilicon Patterning

• Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate
 Step 10: N-diffusion

• Use oxide and masking to expose where n+ dopants should be

diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well contact

n well
p substrate
 Step 10: N-diffusion cont.

• Pattern oxide and form n+ regions

n+ Diffusion

n well
p substrate
 Step 10: N-diffusion cont.

• Historically dopants were diffused

• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+

n well
p substrate
 Step 10: N-diffusion cont.

• Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate
 Step 11: P-diffusion

• Similar set of steps form p+ diffusion regions for pMOS source and
drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate
 Step 12: Contacts

• Now we need to wire together the devices

• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate
 Step 13: Metalization

• Sputter on copper / aluminum over whole wafer

• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field
oxide
p+ n+ n+ p+ p+ n+

n well
p substrate