The CMOS fabrication

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CMOS integrated circuit consists of many individual layers
 polycrystalline silicon (poly),
 silicon dioxide (quartz glass),
 metal conductors

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CMOS processing steps

 Wafer Manufacture
 Oxidation
 Doping
 Photolithography
 Thin-film removal
 Thin-film deposition techniques

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Wafer Manufacture
 Silicon the 2nd most abundant element in the Earth's crust
 most common is silica (impure Si02)
 fabricated on ultrapure, defect-free slices of single crystalline
silicon called wafers
 Metallurgical Grade Silicon (MGS)
 reduction pf silica at 2000C with carbon source
 98% pure silicon
 Si02 (solid) +2C (solid) -> Si (liquid) +2CO (gas)
 Not highly pure
 extremely sensitive to impurity concentrations
 Electronic Grade Silicon (EGS)
 MGS (solid) +HCL (gas) -> silane (SiH4) (liquid) +
trichlorosilane (SiHCL3.) (liquid)
 EGS is polycrystalline

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Wafer Manufacture

Czochralski (CZ) Growth and Wafer Formation

 Gives single crystalline form

 Seed crystal of known
orientation
 growing crystal called boule
or ingot
 pull out rate 1mm/minute
 This cylinder is carefully
sawed into thin disks (wafers).
 The wafers are
later polished and marked
for crystal orientation.

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Finishing

 A chemical mechanical polishing (CMP) process

 Yields a mirror-like finish on one side of the wafer.

 Devices fabricated on the top couple of micrometers

 final wafer thicknesses roughly one millimeter

 (increasing with wafer diameter)

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 Oxidation
Thermal Oxidation

Si + 02 → Si02 (dry oxidation)

Si + 2H20 → Si02 + 2H2 (wet oxidation)

CG = Oxidant concentration in
the bulk gas
Cs = Oxidant concentration at
the surface
Co= Oxidant concentration just
inside the oxide surface
Ci = Oxidant concentration at
the SilSi02 interface

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 Oxidation
Thermal Oxidation

 High temperatures (typically 900 °C-1200 °C)

 dry oxidation denser and higher quality oxide
 wet oxidation higher rate
 Thicknesses limited to few thousand angstroms
 Diffusion Limited thick oxides at high temperatures
 Reaction rate limited thin oxides at low temperatures

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Doping Processes

Dopant impurities required to affect

 Majority carrier type

 Carrier concentration
 Carrier mobility
 Carrier lifetime
 Internal electric fields

Two Methods of doping

 solid state diffusion or simply diffusion
 Ion Implantation preferred in modern CMOS
fabrication

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Ion Implantation

 Ion implantation has the advantage of being a low

temperature and highly controlled process.
 Control on both dopant concentration and junction depth.
 Dopant concentration controlled by ion beam current and
implantation time
 Junction depth by ion energy.

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Ion implantation

Two major steps:

Ion implantation and annealing

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 Diffusion

Diffusion is a natural process where materials move from high

concentration into low-concentration regions driven by the
thermal motion of molecules :temperature about 900 to 12000C.

The junction depth is defined as the point where the diffused

dopant concentration is equal to the substrate concentration

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Photolithography

Photolithography ( lithography or photo ) :

The process that transfers the image of a circuit pattern on
a mask (a photomask) onto the photoresist covering the
wafer surface in order to define various regions

Photoresist:
 radiation-sensitive hydrocarbon
 properties change when exposed to light
 -ve and +ve Photoresist

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(a) positive and (b) negative photoresists

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The Self-Aligned MOSFET

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Implantation of Drain and Source region

L’= L+2L0
effective channel length Leff= L’-2L0

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 Lightly-doped drain (LDD) FETs

used to decrease the channel electric field and reduce hot

electron effects

E at the drain side of a MOSFET= Eapp + Epn

For PN junction having step profile

𝑞𝑁𝑑 𝑥𝑛 𝑞𝑁𝑎 𝑥𝑝
𝐸𝑚𝑎𝑥 = =
𝜀𝑠𝑖 𝜀𝑠𝑖

The LDD structure is designed to decrease the pn junction field by

reducing the doping.

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BITS Pilani, Pilani Campus
 Epitaxial Silicon
The deposition of a thin layer of an ordered crystalline on
top of a single crystalline is known as epitaxy
 Homoepitaxy or
 Heteroepitaxy
 Homoepitaxy widely used in CMOS processes for
performance enhancement

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Twin-Well Process
Define active areas where MOS transistors are to be made
n-well defines pMOS
p-well denes nMOS
The wafer is 1st rinsed and dried to remove contamination and native
oxide.
1.Wafer clean
2.Grown screen oxide 10 to15
nm
3.Photolithography with n-well
mask
4. n-well ion implantation
5. Strip photoresist
6. Wafer clean
7. Anneal and drive in

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 1.Photolithography with
p-well mask
2. p-well ion
implantation
3.Strip photoresist
4.Wafer clean
5.Anneal and drive in
Screen oxide

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Isolation Methods

 Reverse-biased pn junction between transistors

 thick dielectric between transistors, Feld oxide (FOX).
 local oxidation of silicon (LOCOS)
 shallow trench isolation (STI)
 LOCOS thick dielectric of SiO2 500 to 1,000 nm
 LOCOS are encroached into source/drain region
 Isotropic nature of Thermal Oxidation

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shallow trench isolation (STI)
 Used in deep submicron technology
 Has a more accurate vertical profile
 Depth less than 1 μm,
 Used in CMOS processes below 0.25 μm.

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Local oxidation of silicon (LOCOS).

1.Photolithography with active

mask
2. Etch silicon nitride/pad oxide
3. Strip photoresist
4. Wafer clean
5. Isolation implantation for raising
the threshold voltage of the
parasitic MOS transistors

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 (c) Wet oxidation

(d) Strip silicon nitride and pad oxide

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Chemical Vapor Deposition (CVD) Process

A gas mixture is introduced into a reaction chamber where

chemical reactions between gases in the gas mixture at the
surface of wafers produce a desired thin film

Low-pressure CVD (LPCVD) process.

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Threshold Voltage Adjustment

The threshold voltage adjustment is usually done by a low-energy,

low-current ion implantation and performed prior to the gate formation

Explore ?

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Sacrficial oxide with a thickness of about 10 to 20 nm

(b) 1
1.Photolithography with
n-channel VTn (n-select)
mask
2. Ion implantation (Boron)
3. Strip photoresist

phosphorus ions used for pMOS

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 Polysilicon Gate Formation
(a) 1Wafer clean
2.Grow gate oxide 1 to 5
nm
3.Deposit polysilicon 500nm
by LPCVD
4. Doping of polysilicon
5. Deposit ARC (Anti
Reflecting coating)

(b) 1. Photolithography with gate

mask
2. Etch polysilicon
3. Strip photoresist and ARC

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(c) Wafer clean
Polysilicon anneal/oxidation about 9000C

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Source/Drain (S/D) Formation

1.Photolithography with
n-channel S/D (n-select) mask
2.n-channel S/D implantation
Strip photoresist

S/D formation of pMOS transistor

1. Photolithography with
p-channel S/D (p-select) mask
2. p-channel S/D implantation

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Source/Drain (S/D) Formation

(c) Strip photoresist

Wafer clean
Rapid thermal annealing 9000C

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The major steps of contact formation.

(a) Silicon nitride deposition

(b) Oxidation deposition
(c) Lightly doped oxide CVD
(d) PMD(premetal dielectric) deposition by
CVD
(e) PMD polish by CMP(chemical
mechanical polishing)

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The major steps of contact formation.

Photolithography with
contact mask
PMD etching, stop on tisilicide
surface
Photoresist strip
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The major steps of contact formation.

Titanium deposition by PVD

Titanium nitride deposition
Tungsten desposition by CVD
Tungsten polish by CMP

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Formation of Metal1 Interconnect

Titanium deposition (PVD)

TiN deposition (PVD)
Al-Cu alloy deposition (PVD)
TiN deposition (PVD)

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Formation of Metal1 Interconnect

Photolithography with metal1

mask
Etch metal
Strip photoresist
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 Layout Design Rules

Two ways:
lambda (λ) rules and micron (μ) rules
Lambda (λ) rules
function of a single parameter, called λ proposed by Mead and Conway
Micron (μ) rules.
define all rules in absolute dimensions

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Types of Layout Design Rules

Five category:
 minimum width,
 minimum spacing,
 surround,
 minimum extension,
 and exact size, as
shown in Figure

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minimum width rule: The minimum width takes into consideration is
the wire-width limitation of an imaging system and an etching process

minimum spacing :the geometries built on the same mask must

be separated by a minimum spacing so as to fabricate a reliable
feature

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surround rule: When a geometrical feature must be placed inside
an existing geometry, it must be surrounded with a sufficient
margin to guarantee the feature contained by the existing geometry

Minimum extension: Some geometrical

features must extend beyond the edge
of the others by a minimum value

An exact size: means that the feature can only

have the dimensions specied in the layout
design rules
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layout design : Summary

1. Any layout must conform to layout design rules.

2. Layout design rules may be λ based or μ based.

3. The grid in layout editor helps with design rule conformity.

4. The design rule checker (DRC) should be frequently used

to check the layout of a design.

5. A layout plan have to be created and followed in a design.

6. Layouts of cells should have standard locations for inputs,

outputs, power, and ground.

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