Zagazig University

Faculty of Engineering
Electronics and Communications Department

Design of Combinational and Sequential Circuits

Using Verilog

Prepared By:
Ahmed Reda

2014 1
Design of Combinational and Sequential Circuits Using Verilog

Outline
 Introduction
 Verilog Level
 Structure of Program using “Verilog HDL”
 Verilog Operator
 Data type and Number representation
 Control Statement
 Assign and always statements
 Design of Combinational Circuits
 Examples
 Home Work

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Design of Combinational and Sequential Circuits Using Verilog

Introduction

 Hardware design language (HDL) coding for a digital system

 combination circuits
 sequential circuits
 together in any mix.

 Evolution of the HDLs

 Speed up design cycle times for VLSI systems by at least five times

 Two most popular HDLs used currently are Verilog and VHDL
 Are compatible with Altera and Xilinx platform

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Design of Combinational and Sequential Circuits Using Verilog

Introduction (Cont.)

 Verilog has become an industry standard

 its simplicity: you can quickly learn Verilog;
 It has ‘C’ like structure and very fast design cycle times.

 Verilog has been very popular in hi-tech areas of USA, in the

west coast, whereas VHDL is popular in the eastern coast
 Industries prefer Verilog as a means for faster implementation,
whereas institutions prefer VHDL
 Verilog Level
 RTL “Register-transitor-logic”
 Gate level
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Design of Combinational and Sequential Circuits Using Verilog
‫نقوم بوصف الدائره الرقمية بمجرد معرفه عالقة الدخل والخرج‬

Verilog Level

A- Register-transistor-logic "RTL"

‫وهو االكثر شيوعا واستخداما فى وصف‬

‫الدوائر الرقميه‬
‫نقوم بوصف الدائرة الرقمية بمجرد معرفه‬
Ex:- F=A.B+A.C ‫عالقة الدخل والخرج‬

A
B F
Digital circuit
C

Ex:- for Verilog Code

Assign F=(A&B)| (A&C)

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Design of Combinational and Sequential Circuits Using Verilog
‫نقوم بوصف الدائره الرقمية بمجرد معرفه عالقة الدخل والخرج‬

Verilog Level
B-Gate Level

‫نقوم بوصف الدائرة الرقمية عن طريق‬

‫وصف‬
Logic gate
A ‫نفسها‬
x
B g1

C y F
g2 g4
A
B g3 z
C
Ex:- for Verilog Code
And g1 (A,B,x)
And g2 (C,A,y)
And g3 (B,C,z)
Or g4 (x,y,z,F)
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‫‪Design of Combinational and Sequential Circuits Using Verilog‬‬

‫”‪Structure of Program using “Verilog HDL‬‬

‫‪ ‬الخطوات‪-:‬‬
‫‪ ‬تحديد اسم ال ‪ Module‬والى هو هيكون له نفس اسم الدئره الرقميه المراد عملها‬
‫‪ ‬تحديد اسم ال ‪ ports‬الى هيه (الدخل والخرج للدائره )‬
‫‪ ‬تحديد نوعيه ال ‪ port‬نفسه (‪)input ,output, input-output‬‬
‫‪ ‬تحديد عرض ‪ size‬لل ‪ port‬هل هو (‪)wire , Bus‬‬
‫‪ ‬تحديد ‪ Data type‬بمعنى قيمه االشاره الموجوده داخل الدائره هتتخزن فى‬
‫(‪ )Register‬وال أل‬

‫‪2014‬‬ ‫‪7‬‬
Design of Combinational and Sequential Circuits Using Verilog

Structure of Program using “Verilog HDL”

Ex:- describe the following Digital Circuit

Note:- it is required to store the date at outputs x,y

a
x
b
y
c
Test

d z

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Design of Combinational and Sequential Circuits Using Verilog

Structure of Program using “Verilog HDL”

Module test (a,b,c,d,e,x,y,z); All ports must be here
Input a,b; Name of circuit
Input [2,0] c,e; // size can be written [3,1]
Input [1,0] d;
Output x,y;
Output [3,0] z;
Wire a,b;
Wire [2,0] c,e;
Wire [1,0] d;
Reg x,y; // both x and y will be connected by register to save the data
Wire [3,0] z;
..
.. The function of the circuit
..
End Module
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Design of Combinational and Sequential Circuits Using Verilog

Verilog Operator

X=2;
Y=6;
If X>Y // the result will be 0”zero”

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Design of Combinational and Sequential Circuits Using Verilog

Verilog Operator

Concatenation is to convert wire to bus

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Design of Combinational and Sequential Circuits Using Verilog

Data type and Number representation

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Design of Combinational and Sequential Circuits Using Verilog

Control Statement

If (condition ) If (condition ) Case (X)

Begin Begin
.. .. 0: ….
.. .. 1:….
.. .. 2:….
End End 3:….
Else Else if (condition) Default:
Begin Begin ..
.. .. ..
.. .. ..
.. ..
end End End case
Else
Begin
..
..
..
end
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Design of Combinational and Sequential Circuits Using Verilog

Assign and always statements

A- Assign statement A
F
B
‫عاده يستخدم هذا االمر مع ال‬
combinational Circuit
Assign F= A &B;

B-Always statement
‫عاده يستخدم هذا االمر مع ال‬
sequential Circuit and Combinational

always@(..or..or..) always@(A or B)
begin begin
.. F=A&B;
.. end
end
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Design of Combinational and Sequential Circuits Using Verilog

Design of Combinational Circuits:-

You can build any combinational circuit

•Half Adder, Full Adder

•Decoder , Encoder
•MUX, De-MUX
Comparator
•ALU
•Any thing
…
..
.

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Design of Combinational and Sequential Circuits Using Verilog

Examples:-
A- Write a verilog code to impalement the shown circuit

A
B

C F
A
B
C

Solution
A
B F
1-Draw the block of the circuit Cirucit1
C
2-Relation between Input and Output
F=A.B+B.C+C.A

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Design of Combinational and Sequential Circuits Using Verilog

Examples:-
3-The code

Module Circuit 1 (A,B,C,F);

Input A,B,C;
Output F;
Wire A,B,C,F;

always @ (A or B or C)
begin
F = (A&B)|(B&C)|(C&A);
End

End Module

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Design of Combinational and Sequential Circuits Using Verilog

Examples:-
B- Write a verilog code to impalement the Full Adder

Solution

1-Draw the block of the circuit

A
B Sum
2-Relation between Input and Output, Full Adder
Cin
You should build the truth table Cout

A B Cin Cout Sum

Sum= A ^B^Cin
Cout= (A ^B).Cin +A.B

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Design of Combinational and Sequential Circuits Using Verilog

Examples:-
3-The code

Module Full Adder (A,B,Cin,Sum,Cout);

Input A,B,Cin;
Output Sum, Cout;
Wire A,B,Cin,Sum,Cout;

always @ (A or B or Cin)
begin
Sum= X ^Y^Cin;
Cout= ((A ^B)&Cin) | (A&B);

End

End Module

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Design of Combinational and Sequential Circuits Using Verilog

Examples:-
C- Write a verilog code to impalement the Mux 4*1

Solution

1-Draw the block of the circuit A

B F
2-Relation between Input and Output, MUX 4*1
C
You should build the truth table
D

S1 S2

There are a lot of method to do that

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Design of Combinational and Sequential Circuits Using Verilog

Examples:-
3-The code

Module MUX(A,B,C, D, S1,S2,F);

Input A,B,C,D,S1,S2;
Output F;
Wire A,B,C,D,S1,S2, F;

always @ (A or B or C or D or S1 or S2)
begin
case ({S1 , S2})

2'b00: F= A ;
2‘b01: F=B;
2'b10: F= C ;
2'b11: F= D ;
default:
F=0;
endcase
end
End Module 2014 21
Design of Combinational and Sequential Circuits Using Verilog

Home Work:-

2014 22