Interfacing Devices

Interfacing devices
 8255 Programmable peripheral
Interface(PPI)
• 8255 is a popularly used parallel,
programmable input-output device.
• It can be used to transfer data under various
condition from simple input-output to
interrupt input-output.
• This is economical, functional, flexible but is a
little complex and general purpose i/o device
that can be used with almost any
microprocessor.
 Features of 8255A

• The 8255A is a general purpose programmable

I/O device designed to transfer the data from I/O
to interrupt I/O under certain conditions as
required.
• It can be used with almost any microprocessor.
– The prominent features of 8255A are as follows −
• It consists of three 8-bit bidirectional I/O ports (24 I/O lines)
which can be configured as per the requirement.
• i.e. PA, PB, and PC.
• Address/data bus must be externally demux'd.
• It is TTL compatible.
• It has improved DC driving capability.
 8255 pin diagram
• It has 24 pins that can be grouped in two 8-bit
parallel ports:
• A and B called Port A(PA) and Port B(PB)
• The remaining eight known as Port C(PC).
• Port C can be further divided into groups of 4-
bits ports named Cupper(Cu) and Clower(Cl).
• There are 40 pins
• It operated in +5 regulated power supply.
8255 pin diagram
 8255 Architecture
• The following figure shows the architecture of
8255A
8255 Architecture
 8255 Architecture
• Ports of 8255A
– 8255A has three ports, i.e., PORT A, PORT B, and
PORT C.
• Port A contains one 8-bit output latch/buffer
and one 8-bit input buffer.
• Port B is similar to PORT A.
• Port C can be split into two parts,
– i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.
 8255 Architecture
• Data Bus Buffer
– It is a tri-state 8-bit buffer, which is used to interface the
microprocessor to the system data bus.
– Data is transmitted or received by the buffer as per the
instructions by the CPU.
– Control words and status information is also transferred
using this bus.
• Read/Write Control Logic
– This block is responsible for controlling the
internal/external transfer of data/control/status word.
– It accepts the input from the CPU address and control
buses, and in turn issues command to both the control
groups.
 8255 Architecture
• CS
– It stands for Chip Select. A LOW on this input
selects the chip and enables the communication
between the 8255A and the CPU. It is connected
to the decoded address, and A0 & A1 are
connected to the microprocessor address lines.
 8255 Architecture

CS A1 A0 Result
0 0 0 PORT A
0 0 1 PORT B
0 1 0 PORT C
0 1 1 Control
Register
1 X X No Selection
 8255 Architecture
• WR
– It stands for write. This control signal enables the
write operation.
– When this signal goes low, the microprocessor writes
data into a selected I/O port or control register.
– This input pin enables the CPU to write data or control
words into the 8255.
• RESET
– This is an active high signal.
– It clears the control register and sets all ports in the
input mode.
 8255 Architecture
• RD
– It stands for Read.
– This control signal enables the Read operation.
– When the signal is low, the microprocessor reads the data
from the selected I/O port of the 8255.
– This input pin enables 8255 to send the data or status
information to the CPU on the data bus.
• A0 and A1
– These input signals work with RD, WR, and one of the
control signal.
– Following is the table showing their various signals with
their result.
 8255 Architecture
A1 A0 RD WR CS Result
Input Operation
PORT A → Data Bus
0 0 0 1 0

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
Data Bus → PORT A
0 0 1 0 0

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

 Operating Modes

• Modes of 8255 – It works in two modes:

– Bit set reset (BSR) mode
– Input/output (I/O) mode
• To know in which mode the interface is
working we need to know the value of Control
word.
• Control word is a part of control register in
8255 which specify an I/O function for each
port.
control word 8255.
 8255 PPI
• To communicate with peripherals through
8255 three steps are necessary:
– Determine the addresses of Port A, B, C and
Control register according to Chip Select Logic and
the Address lines A0 and A1.
– Write a control word in control register.
– Write I/O instructions to communicate with
peripherals through port A, B, C.
 Operating Modes
• If the most significant bit of control word or
D7 is 1 then 8255 works in I/O mode else, if
it’s value is 0 it works in BSR mode.
• BSR Mode – When MSB of the control register
is zero(0), 8255 works in Bit Set-Reset mode.in
this only PC bit are used for set and reset.
• I/O Mode – When MSB of the control register
is one(1), 8255 works in Input-Output mode.it
is further divided into three categories.
 Operating Modes

– Mode 0
• In this mode, Port A and B is used as two 8-bit ports
and Port C as two 4-bit ports.
• In this mode all three ports (PA, PB, PC) can work as
simple input function or output function.
• Each port can be programmed in either input mode or
output mode where outputs are latched and inputs are
not latched.
• Ports do not have interrupt capability.
 Operating Modes

– Mode 1 − In this mode, Port A and B is used as 8-

bit I/O ports. They can be configured as either
input or output ports.
– Each port uses three lines from port C as
handshake signals before actual data transmission
plus it has interrupt handling capabilities.
– Inputs and outputs are latched.
 Operating Modes
• Mode 2 − In this mode, Port A can be configured as
the bidirectional port and Port B either in Mode 0 or
Mode 1.
• Port A uses 6 bits from Port C as handshake signals
for data transfer plus it also has to interrupt handling
capability.
• The remaining three signals from Port C can be used
either as simple I/O or as handshake for port B.
 8255 PPI
• The common applications of 8255 are:
– Traffic light control
– Generating square wave
– Interfacing with DC motors and stepper motors
 Architecture of 8259
• MicrocontrollerMicroprocessor8085
• 8259 Microprocessor is architected in a unique style. It can program by means of
some interrupts conditions by means of level or interrupt level often called edge
triggered interrupt level. Masking is done to individual interrupt bits. As the
number of 8259 increases interrupt pins up to 64 can be obtained. There are 3
registers 8259 contains along with one priority resolver(PR). They are as follows:
• Interrupt Request Register(IIR) - It stores the bits who requests the interrupt.
• Interrupt service register(ISR) - It stores the currently interrupt levels.
• Interrupt Mask Register(IMR) -Stores the interrupt levels to be masked.
• PriorityResolver(PR) - Set the priority of interrupts by examining all the three
registers and set the interrupt level inISR having the highest priority.
• SP/EN (low active pin) - When its value is 1 it works in master mode and when its
value is 0 it works in slave mode.
• Cascade Buffer - Used for cascading more Programmable Interrupt Controlle
 8259A Interrupt controller
• Instead of using a NAND gate and a latch, the
interrupt mechanism is usually implemented
with a more advanced digital device – Interrupt
controller
• 8259A is a typical example
• 8259A is a hardware device to support the
interrupt mechanism
• It can support up to 8 vectored priority encoded
interrupts to the microprocessor
• Can be expanded (using more 8259) to accept
up to 64 interrupt requests using master/slaves
configuration
 8259A programmable interrupt controller
• 8259A is programmed via the microprocessor
through the host processor interface
• The host interface consists of: data bus, read,
write, interrupt request (INT), interrupt
acknowledge (INTR) and chip select
• The data can be command words, status
information, or interrupt type numbers.
• The INT and INTR are connected to the
microprocessor. They are used for handshaking
 Pins assignment for 8259A

Interrupt
Comm. input
with from external
CPU devices

Control Cascade
signals for multiple
8259A setup
 Interrupt controller
• INT generated by 8259 is connected to INTR
of 8086
• INT =1 when 8259 receives a valid interrupt
request
• INTA produced by the microprocessor
consists of two pulse and it signals the 8259
to put the interrupt type number on the
data bus
Interfacing the 8259A to 8086

Cascading
Using master
Slave connection
This is a PAL
From the CPU’s point of
View, the 8259 is also a
I/O device!!!!

How the 8259 is enabled?

Block Diagram of 8259A
 Interrupt mask register
• Interrupt mask register (IMR) can be used to
enable or mask out individually the interrupt
request inputs
• There are 8 bits and each bit represents one
interrupt input
• 0- enable; 1- mask out (disable)
• The register can be read from or written into
under software control (programmed via the
microprocessor
 Interrupt request register (IRR)
• IRR stores the current status of the interrupt
request inputs
• Has one bit for each IR input
• The values in the bit positions reflect whether
the interrupt inputs are active or inactive
 Priority resolver
• The priority resolver identifies which of the active
interrupt inputs has the highest priority
• The resolver can be configured to work using a
number of different priority schemes through
software
• It will signal the control logic that an interrupt is
active and in response, the control logic causes
the INT signal to be issued
 8259 interrupt controller
• The in-service register (ISR) stores the interrupt
level that is presently being serviced.
• During the first INTA pulse in an interrupt
acknowledge bus cycle, the level of the highest
active interrupt is strobed into ISR.
• The ISR cannot be written into by the
microprocessor but its contents may be read as
status
• The cascade buffer/comparator section provides
the interface between master and slave 8259As.
This permits easy expansion of the interrupt
interface using a master/slave configuration
Connecting two 8259A
 Master/slave

SP/EN – 1 (master); 0 (slave)

 Summary
• Using interrupt allows CPU to serve many devices
at the same time
• Different types – software, hardware
• Interrupt – has priority. Always serve the high
priority first
• ISR – interrupt service routine tells the CPU what
to do during an interrupt
• A table stores the locations (represented by the
corresponding CS and IP values) of the ISRs
 Summary
• INTR, NMI are inputs for external interrupt
• INTA – output to acknowledge the interrupt
and ask for the interrupt vector
• Interrupt controller is to expand the interrupt
interface, resolve priority etc