Unit 5: Initialization of 80386DX

Initialization
• After a signal on the RESET pin, certain
registers of 80386 are set to predefined values
• These values are adequate to enable
execution of a bootstrap program.
 Processor State after RESET
• Contents of EAX depends on results power-up self test
• Self-test may be requested externally by assertion of BUSY# at
the end of RESET (EAX=0 if the 80386 passed the test, else
80386 unit is faulty)
• If self-test is not requested , EAX is undefined
• DX holds a component identifier and revision number (DH=3,
indicates 80386, DL=unique identifier of the revision level)
• Control Register 0 (CR0) contains
 Software initialization for Real-
address mode
• In real-address mode a few structures must be
initialized
– Stack: No instructions that use the stack can be used until
the stack-segment register (SS) has been loaded. SS must
point to an area in RAM.
– Interrupt table: Initially interrupts are disabled, but in case
of an exception and NMI, interrupt table may be accessed.
Initialization software should take one of the following
actions:
• Change the limit value in the IDTR to zero, causing shutdown in
case of exception or NMI
• Put Pointers to valid interrupt handlers in all positions of the
interrupt table that might be used by exception or interrupt
• Change the IDTR to point to a valid interrupt table.
– First Instruction: FFFFFFF0H
 Switching to Protected Mode
• Setting PE bit of the MSW in CR0
• The CPL starts at zero
• Segment registers continue point to the same
linear addresses as in real address mode
• Immediately after setting PE bit, the initialization
code must flush the processor’s instruction
prefetch queue by executing JMP instruction
• The 80386 fetches and decodes instructions and
addresses before they are used
 Software initialization for Protected
Mode
• Most of the initialization needed for protected
mode can be done either before or after
switching
• The initialization procedures must not use
protected-mode features that are not yet
initialized
 Initializing IDT
• The IDTR may be loaded in either real-address or
protected mode.
• However, the format of the interrupt table for protected
mode is different than that for real-address mode.
• It is not possible to change to protected mode and
change interrupt table formats at the same time;
therefore, it is inevitable that, if IDTR selects an
interrupt table, it will have the wrong format at some
time. An interrupt or exception that occurs at this time
will have unpredictable results.
• To avoid this unpredictability, interrupts should remain
disabled until interrupt handlers are in place and a valid
IDT has been created in protected mode.
 Stack initialization
• The SS register may be loaded in either real-
address mode or protected mode.
• If loaded in real-address mode, SS continues
to point to the same linear base-address after
the switch to protected mode
 Global Descriptor Table initialization
• Before any segment register is changed in
protected mode, the GDT register must point
to a valid GDT.
• Initialization of the GDT and GDTR may be
done in real-address mode.
• The GDT (as well as LDTs) should reside in
RAM, because the processor modifies the
accessed bit of descriptors
 Page Tables initialization
• Page tables and the POBR in CR3 can be initialized in
either real-address mode or in protected mode;
• however, the paging enabled (PG) bit of CRO cannot be
set until the processor is in protected mode.
• PG may be set simultaneously with PE, or later.
• When PG is set, the PDBR should already be initialized
with a physical address that points to a valid page
directory.
• initialization procedure should adopt one of the
following strategies
– The page that is currently being executed should map to the
same physical addresses both before and after PG is set
– A JMP instruction should immediately follow the setting of
PG.
 First task initialization
Before the first task switch, the following conditions
must prevail:
• There must be a valid task state segment (TSS) for
the new task. The stack pointers in the TSS for
privilege levels numerically less than or equal to
the initial CPL must point to valid stack segments.
• The task register must point to an area in which
to save the current task state. After the first task
switch, the information dumped in this area is
not needed, and the area can be used for other
purposes.
 TLB Testing
• The 80386 provides a mechanism for testing
the Translation Lookaside Buffer (TLB), the
cache used for translating linear addresses to
physical addresses.
• When testing the TLB it is recommended that
paging be turned off (PG=0 in CR0) to avoid
interference with the test data being written
to the TLB.
 Structure of TLB
• TLB is a four-way set-
associative memory
• There are four sets of eight
entries each.
• Each entry consists of a tag
and data.
• Tags are 24-bits wide. They
contain the high-order 20 bits
of the linear address, the
valid bit, and three attribute
bits.
• The data portion of each
entry contains the high-order
20 bits of the physical
address.
 Test Registers
• Two test registers are provided for the purpose of
testing.
• TR6 is the test command register, and TR7 is the test
data register.
• The test registers are privileged resources; in
protected mode, the MOV instructions that access
them can only be executed at privilege level 0.
 The Test Command Register (TR6) (1)

• C: Command bit, two commands: ‘0’- write

entries into the TLB and ‘1’ perform TLB
lookups
• Linear Address:
– on a TLB write command, a TLB entry is allocated
to this linear address and the rest of that TLB
entry is set as per the values of TR7 & TR6
– on a TLB lookup command, the TLB is interrogated
as per this value and if one and only one TLB entry
matches, the rest of the fields of TR6 & TR7 are
set from the matching TLB entry.
 TR6 (2)

• V: The Valid bit for this TLB entry. The TLB uses the
valid bit to identify entries that contain valid data.
Entries of the TLB that have not been assigned values
have zero in the valid bit. All valid bits can be cleared
by writing to CR3.
• D, D#: The dirty bit for/from the TLB entry
• U, U#: The U/S bit for/from the TLB entry
• W, W#: The R/W bit for/from the TLB entry
Meaning of D, U, and W Bit Pairs
 The Test Data Register (TR7)
Holds data read from or data to be written to the TLB
• Physical Address: This is the data field of the TLB. On a
write to the TLB, the TLB entry allocated to the linear
address in TR6 is set to this value. On a TLB lookup, if HT
is set, the data field (physical address) from the TLB is
read out to this field. If HT is not set, this field is
undefined.
• HT: For a TLB lookup, the HT bit indicates whether the
lookup was a hit (HT <- 1) or a miss (HT <- 0). For a TLB
write, HT must be set to 1.
• REP: For a TLB write, selects which of four associative
blocks of the TLB is to be written. For a TLB read, if HT is
set, REP reports in which of the four associative blocks
the tag was found; if HT is not set, REP is undefined.
 Test Operations
• To write a TLB entry
– Move a doubleword to TR7 that contains the desired
physical address, HT, and REP values. HT must contain 1.
REP must point to the associative block in which to place
the entry
– Move a doubleword to TR6 that contains the appropriate
linear address, and values for V, D, U, and W. Be sure C=0
for "write" command.
• To look up (read) a TLB entry
– Move a doubleword to TR6 that contains the appropriate
linear address and attributes. Be sure C = 1 for "lookup"
command
– Store TR 7. If the HT bit in TR 7 indicates a hit, then the
other values reveal the TLB contents. If HT indicates a miss,
then the other values in TR 7 are indeterminate
DEBUGGING
 Introduction
• significant advances in debugging power
• single-step exception and breakpoint
exception of previous processors are still
available
• but the principal debugging support takes the
form of debug registers
• debug registers support both instruction
breakpoints and data breakpoints
 Debugging Features of the
Architecture
• Reserved debug interrupt vector
• Four debug address registers
• Debug control register
• Debug status register
• Trap bit of TSS (T-bit)
• Resume flag (RF) of flags register
• Single-step flag (TF)
• Breakpoint instruction
• Reserved interrupt vector for breakpoint
exception
• The debugger can be invoked under any of the
following kinds of conditions:
– Task switch to a specific task.
– Execution of the breakpoint instruction.
– Execution of every instruction.
– Execution of any instruction at a given address.
– Read or write of a byte, word, or doubleword at any
specified address.
– Write to a byte, word, or doubleword at any specified
address.
– Attempt to change a debug register.
 Debug Registers
• Six registers: to control debug features
• Accessed by variants of the MOV instruction
• debug registers are privileged resources
• Registers are:
– Debug Address Registers (DRO-DR3)
– Debug Control Register (DR7)
– Debug Status Register (DR6)