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FET Biasing

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Introduction
 For the JFET, the relationship between input and output
quantities is nonlinear due to the squared term in
Shockley’s equation.
 Nonlinear functions results in curves as obtained for
transfer characteristic of a JFET.
 Graphical approach will be used to examine the dc
analysis for FET because it is most popularly used rather
than mathematical approach
 The input of BJT and FET controlling variables are the
current and the voltage levels respectively

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Introduction
JFETs differ from BJTs:

 Nonlinear relationship between input (VGS) and output (ID)


 JFETs are voltage controlled devices, whereas BJTs are
current controlled

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Introduction
Common FET Biasing Circuits
• JFET
– Fixed – Bias
– Self-Bias
– Voltage-Divider Bias

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General Relationships
 For all FETs:
IG  0A
ID  IS

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Fixed-Bias Configuration
 The configuration includes the ac levels Vi and Vo and
the coupling capacitors.
 The resistor is present to ensure that Vi appears at the
input to the FET amplifier for the AC analysis.

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Fixed-Bias Configuration
 For the DC analysis,
 Capacitors are open circuits
 I  0 A and V
G RG  I G RG  (0 A) RG  0V
 The zero-volt drop across RG permits replacing RG by a short-circuit

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Fixed-Bias Configuration
Investigating the input loop
 IG=0A, therefore
VRG=IGRG=0V
 Applying KVL for the input loop,
-VGG-VGS=0
VGG= -VGS
 It is called fixed-bias configuration due to VGG is a fixed
power supply so VGS is fixed V
ID  IDSS (1  GS
)2
 The resulting current, VP
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 Investigating the graphical approach.
 Using below tables, we
can draw the graph
VGS ID
0 IDSS
0.3VP IDSS/2
0.5 IDSS/4
VP 0mA

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 The fixed level of VGS has been superimposed as a
VGS  VGG
vertical line at
 At any point on the vertical line, the level of VG is -VGG---
the level of ID must simply be determined on this vertical
line.
 The point where the two curves intersect is the common
solution to the configuration – commonly referrers to as
the quiescent or operating point.
 The quiescent level of ID is determine by drawing a
horizontal line from the Q-point to the vertical ID axis.
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 Output loop
V DS  V DD  I D R D
VS  0V
V DS  VD  VS
V D  VDS  VS VS  0

VD  VDS
VGS  VG  VS
VG  VGS  VS VS  0

VG  VGS

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Example
 Determine VGSQ, IDQ, VDS, VD, VG, VS

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Exercise
 Determine IDQ, VGSQ, VDS, VD, VG and VS

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Self Bias Configuration
 The self-bias configuration eliminates the need for two
dc supplies.
 The controlling VGS is now determined by the voltage
across the resistor RS

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 For the indicated input loop:
VGS   I D RS
 Mathematical approach:
2
 VGS 
ID 
 I DSS 1  
 VP 
2
 I D RS 
ID  I DSS 1  
 VP 
 rearrange and solve.

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 Graphical approach
 Draw the device transfer characteristic
 Draw the network load line
 Use VGS  to
 I draw
D RS straight line.
 First point, I D  0, VGS  0
 Second point, any point from ID = 0 to ID = IDSS. Choose

I DSS
ID  then
2
I R
VGS   DSS S
2

 the quiescent point obtained at the intersection of the


straight line plot and the device characteristic curve.
 The quiescent value for ID and VGS can then be determined
and used to find the other quantities of interest.
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17
 For output loop
 Apply KVL of output loop
 Use ID = IS

V DS  V DD  I D ( RS  R D )
VS  I D RS
V D  V DS VS  V DD V RD

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19
Example
 Determine VGSQ, IDQ,VDS,VS,VG and VD.

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Example
 Determine VGSQ, IDQ, VD,VG,VS and VDS.

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Voltage-Divider Bias
 The arrangement is the same as BJT but the DC analysis is different
 In BJT, IB provide link to input and output circuit, in FET VGS does
the same

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Voltage-Divider Bias
 The source VDD was separated into two equivalent sources to permit
a further separation of the input and output regions of the network.
 IG = 0A ,Kirchoff’s current law requires that IR1= IR2 and the series
equivalent circuit appearing to the left of the figure can be used to
find the level of VG.

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Voltage-Divider Bias
 VG can be found using the voltage divider rule :
R2VDD
VG 
R1  R2

 Using Kirchoff’s Law on the input loop:


 Rearranging
VGand
VGS using
V RS  ID
0 =IS:
VGS  VG  I D RS

 Again the Q point needs to be established by


plotting a line that intersects the transfer curve.
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Procedures for plotting

1. Plot the line: By plotting two points: VGS = VG, ID =0 and VGS = 0, ID = VG/RS
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID. 25

3. Where the line intersects the transfer curve is the Q point for the circuit.
 Once the quiescent values of IDQ and VGSQ are determined, the
remaining network analysis can be found.
V DD
I R1  I R 2 
R1  R2

 Output loop: VDS  VDD  I D ( RD  I D RS )


V D  V DD  I D R D

VS  I D RS

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Effect of increasing values of RS

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Example
 Determine IDQ, VGSQ, VD, VS, VDS and VDG.

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Example
 Determine IDQ, VGSQ, VDS, VD and VS

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=-
= -

=-
= - ( + )

=
+
= -
= - ( + )

= -
= + - ( + )

=
30
=

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