High-Level Synthesis

of VLSIs

林永隆 (Youn-Long Lin)

Department of Computer Science
National Tsing Hua University

THEDA Tsing Hua Electronic Design Automation

 VLSI Design Tools
• Design Capturing/Entry
• Analysis and Characterization
• Synthesis/Optimization
– Physical (Floor planning, Placement, Routing)
– Logic (FSM, Retiming, Sizing, DFT)
– High Level(RTL, Behavioral)
• Management

2
Design Methodology Progress
Specify and ???

Describe and Synthesis

Capture and Simulate

3
Why Synthesis? Why not Synthesis?

Productivity Performance Loss

Correctness Unsynthesizability

Re-Targetability Inertial

4
 Structural Behavioral
Block Algorithm
RTL FSM
Boolean
Gate
X’tor

GDSII

Placement
Y-Chart
Dan D Gajski Floorplan

Physical
5
 Structural Behavioral
Block Algorithm
RTL FSM
Boolean
Gate
X’tor

GDSII

Layout Placement
Synthesis
Floorplan

Physical
6
 Structural Behavioral
Block Algorithm
RTL FSM
Boolean
Gate
X’tor

GDSII

Logic Placement
Synthesis
Floorplan

Physical
7
 Structural Behavioral
Block Algorithm
RTL FSM
Boolean
Gate
X’tor

GDSII

High-Level Placement
Synthesis
Floorplan

Physical
8
 High Level Synthesis

Behavioral
Description
Parsing

CDFG Synthesis
Structural
RTL
Transformation

9
 What Went Wrong?
• Too much emphasis on incremental work
on algorithms and point tools
• Unrealistic assumption on component
capability, architectures, timing, etc
• Lack of quality-measurement from the low
level
• Too much promising on fully automation
(silicon compiler??)
10
 Essential Issues
• Behavioral Specification Languages
• Target Architectures
• Intermediate Representation
• Operation Scheduling
• Allocation/Binding
• Control Generation

11
 Behavioral Specification
Languages
• Add hardware-specific constructs to
existing languages
– HardwareC
• Popular HDL
– Verilog, VHDL
• Synthesis-oriented HDL
– UDL/I

12
 Target Architectures
• Bus-based
• Multiplexer-based
• Register file
• Pipelined
• RISC, VLIW
• Interface Protocol

13
Delay Design Space Exploration

Arch I

Arch II

Arch III

Area 14
FSM with Data Path (FSMD)

Data
FSM
Path

Interactive FSMDs

Data Data
FSM FSM
Path Path

15
Intermediate Representation

* *
+

Data Flow Graph

16
Control Flow Graph
 Scheduling
(Temporal Binding)
• Time & Resource Tradeoff
• Time-Constrained
– Integer Linear Programming (ILP)
– Force-Directed
• Resource-Constrained
– List Scheduling
• Other Heuristics
– Simulated Annealing, Tabu Search, ...
17
 Allocation/Binding

Operations Functional Units

Variables
Storage
Signals

Data Transfers Bus/Wire/Mux

18
 Variables/Signals
RF RF
Data Transfer

FU
FU

Operations 19
Controller Specification
Generation

Scheduled
CDFG
Micro-Operations
for
Every Control Step
Allocated
Datapath

20
 HLS Quality Measures
• Performance
• Area Cost
• Power Consumption
• Testability
• Reusability

21
 Hardware Variations
• Functional Units
– Pipelined, Multi-Cycle, Chained, Multi-
Function
• Storage
– Register, RF, Multi-Ported, RAM, ROM,
FIFO, Distributed
• Interconnect
– Bus, Segmented Bus, Mux, Protocol-Based
22
 Functional Unit Variations

Step 1
+ +
* + *
Step 2
+ +
*
Step 3
-
Step 4
*
23
 Storage/Interconnect
Variations
RF RF
Multi-Port Segmented
Buses

Mux Distributed
FIFO
FU
FU
24
Chaining
Architectural Pipelining

Data
FSM
Path

25
 THEDA’s Work on HLS
• ILP-based Scheduling
• Bipartite Weighted Matching for Datapath
Allocation
• Performance-Driven Interconnect Synthesis
• Loop Folding & Retiming
• Integrating Synthesis and Layout
• DSP Core Generation
• Book on HLS
26
Integer Linear Programming
for Scheduling
• Given # Control Steps
• ASAP + ALAP ==> Possible Steps for each
Operations
• Tight Constraints on
– Dependency
– One Scheduled Step per Op
– Resource Usage per Step
• Many Extensions
27
Advanced Scheduling for
Loop Folding
1

2
2

3
3

28
Loop Folding(cont.)

Prologue
1

2 Folded Body

3
Epilogue

29
 Retiming and Loop Folding
A B C D E F A B C D E F

1 1

E A B E C A
2 2
F D C F D B

3 3

30
Integrating Layout and Synthesis
HDL Description P&R

HDL Synthesis RC Extraction &

Delay Calculation
Soft-Macro
Formation Post-Layout
Timing Analysis
Block Placement Timing Ok & no more
area improvement

No
Soft-Macro
Module Resynthesis
Placement
Chip Layout 31
 HLS Techniques for DSP Code
Generation

Memory Allocation

Address Generation Scheduling

32
 Applications of HLS
Technology
• Code generation for embedded
processors
• Retargetable compilers for application-
specific instruction-set processors
(ASIP)
• Reconfigurable computing
• Advanced features in logic synthesizer

33
 System-on-a-Chip

Processor Memory Wireless

External

Bridge

USB
Memory
Interface

Bus Master IP UART

34
 SOC with PLDs

Processor Memory Wireless

External

Bridge

USB
Memory
Interface

Bus Master FPGA FPGA

35
 System
Houses/ Wafer
IC Vendors Foundry
(Fabless)

Library/
IP
Vendors Integrators
(Chipless)

EDA
Vendors
Paradigm Shift 36
 IP and Synthesis
• Authoring IP for Synthesis
• Synthesis utilizing IP
• Synthesizing IPs

Executable Data Sheets

37
Executable Data Sheets

More than
IP Wrapper just the
Port Interface

IP

38
 Future Directions
• Realistic Methodology
– Evolutional Transition from Current Practice
– Domain Specific
• IP-Centric
– As both Authoring Aid and Integrator
• Software
– Co-design and Code Generation

39
 IC
Value

IP

EDA

Time 40