Chapter: 7

Memory and I/O interfacing with 8085/8086

 What is an Interface
• Is a shared inter connection between two or more
device with a clear understanding of the signal
exchanging through it.
• an interface is a concept that refers to a point of
interaction between components, & is applicable at
the level of both hardware & software.
• This allows a component, (such as a graphics card
or an Internet browser), to function independently
while using interfaces to communicate with other
components via an input/output system & an
associated protocol.

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3
Example: Block Diagram

Address Lines

Data Lines
8085 Memory

Control Lines

Interface
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 8085 Interfacing Pins

Higher Address Bus A15 – A8

Lower Address/Data Bus AD7 – AD0

8085 ALE
IO/ M
RD
WR
READY

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 Address Bus of 8085
• Address Bus
– Used to address memory & I/O devices
– 8085 has a 16-bit address bus
Higher-order Address Lower-order Address
A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

 Data Bus Data Bus

 Used to transfer instructions & data
 8085 has a 8-bit data bus
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Higher Order Address Bus
• The higher order address bus is a unidirectional bus.
• It carries most significant 8-bits of a 16-bit address of
memory or I/O device.
• Address remains on lines as long operation is not
completed.
Lower Order Address/Data Bus
• This bus is bidirectional & works on time division
multiplexing between address & data.
• During first clock cycle, it serves as a least significant 8-
bits of memory/ IO address.
• For second & third clock cycles it acts as data bus &
carries data.
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 Demultiplexing Address/Data
Lines
• 8085 identifies a memory location with its 16 address
lines, (AD0 to AD7) & (A8 to A15)
• 8085 performs data transfer using its data lines, AD0 to
AD7
• Lower order address bus & Data bus are multiplexed on
same lines i.e. AD0 to AD7.
• Demultiplexing refers to separating Address & Data
signals for read/write operations.

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 Generating Control Signals
Generating Memory read Signal
IO/ M =0
1 Memory Read
RD=0 1
1 Memory Write
WR=1 0
0 IO Read
1
0 IO Write
0
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 Generating memory write Signal
IO/ M =0
1 Memory Read
RD=1 0
1 Memory Write
WR=0 1
0 IO Read
0
0 IO Write
1
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 Generating IO Read Signal
IO/ M =1
0 Memory Read
RD=0 1
0 Memory Write
WR=1 0
1 IO Read
1
1 IO Write
0
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 Generating IO Write Signal
IO/ M =1
0 Memory Read
RD=1 0
0 Memory Write
WR=0 1
1 IO Read
0
1 IO Write
1
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 Memory Interface
• The memory is made up of semiconductor material used to store
the programs & data. The types of memory is,
– Primary or main memory
– Secondary memory
Primary Memory
• RAM & ROM are examples of this type of memory.
• Microprocessor uses it in storing a program temporarily
(commonly called loading) & executing a program.
• Hence the speed of this type of memory should be fast.
Secondary Memory
• These are used for bulk storage of data & information.
• The main examples include Floppy, Hard Disk, CD-ROM,
Magnetic Tape etc.
• Slower & Sequential Access Nature.
• non-volatile nature.
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 Memory Chip
‘k’ data input lines
‘n’ address lines
Memory Chip select
read 2 words
n

write ‘k’ bits per word

‘k’ data output lines

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8085 Interfacing with Memory chips

Data

74LS373 Program
8085 AD0-AD7 A0 – A7
ALE
Memory
A8-A15 A8-A15
CS
IO/M
RD
RD
Memory
Interface

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 Interface with two memory chips
A1
A0
11 11
10 10
01 01
00 00
Memory 1 Memory 2
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 Interface with two memory chips
A1
A0
11 011 11 111
10 010 10 110
01 001 01 101
00 000 00 100
A3 CS CS
Memory 1 Memory 2 17
 Interface with Multiple Chips
• In case of multiple chips simple circuit like
NOT gate will not work.
• In this case normally decoder circuits like
3-to-8 decoder circuit 74LS138 are used.
• These circuit are called address decoders.

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 Address decoders
2 to 4 decoder
O0 CS Memory 1
A12 S1 O1 CS Memory 2
A11 S0 O2 CS Memory 3
O3 CS Memory 4
E
A13
A10 - A0
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 Address Decoding Techniques
• Decoding logic: it is the logic circuit in the mother board
which will suitable select or deselect ICs according to the
address & control signals generated.
• Decoder logic can be gates or decoders
• There are two types of decoding technique depending on
the number of lines used for the decoder.
 Full or absolute decoding
 Partial decoding

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• In full decoding, all remaining address lines are
used for the decoder to generate chip select signal
for the memories. i.e. In this type of scheme all the
16 bits of the 8085 address bus are used to select a
particular location in memory chip.

• But in partial decoding, In this scheme minimum

number of address lines are used as required to
select a memory location in chip.

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Contd.

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 Memory interfacing steps
1. Understand the memory requirement clearly. i.e. the type of
memory, the capacity of the chips & the address where it
has to be interfaced.
2. Draw a memory map(table of addresses).
3. Decide, how many address lines has to be connected to the
memory ICs.
4. Out of the 16 address lines, find how many address lines are
not connected to the memory ICs.(remaining address lines).
5. Generate chip select signal[decoder logic] using the
remaining address lines(but while doing this we should see
that there is no conflict(i.e. no two ICs should be selected at
the same time).
6. Generate & connect appropriate control signals to memory ICs.
(MEMR,MEMW) 23
 Example
• Draw the circuit diagram of an 8085 system, having a 4
KB EPROM and two 8 KB RAM ICs. The starting
address of the EPROM is 0000H and that of RAM-I
4000H and RAM-II 8000H. The address of the decoder
circuits should be clearly shown.
 Solution
• EPROM - 4 KB (Address lines required is 12 – A0 to A11 )
• RAM-I - 8 KB (Address lines required is 13 – A0 to A12 )
• RAM-II - 8 KB (Address lines required is 13 – A0 to A12 )

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Mapping of Addresses to Memory ICs

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The complete interfaced circuit diagram

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 Exercises
1. Design an interface circuit to interface 8K RAM
and 8K EPROM at the following addresses to
the 8085 processor. Use absolute decoding
technique.
The starting address of the EPROM is 0000H and
that of RAM 2000H

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 Interfacing I/O Devices
• Using I/O devices data can be transferred
between the microprocessor & the outside world.
• This can be done in groups of 8 bits using the
entire data bus. This is called parallel I/O.
• The other method is serial I/O where one bit is
transferred at a time using the SID & SOD pins
on the Microprocessor.

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Types of Parallel Interface(Addressing the I/O devices)
• There are two ways to interface 8085 with I/O devices in
parallel data transfer mode:
– Memory Mapped IO
– IO Mapped IO
Memory Mapped IO
• It considers them like any other memory location.
– They are assigned a 16-bit address within the
address range of the 8085.
– The exchange of data with these devices follows
the transfer of data with memory. The user uses
the same instructions used for memory.
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 Cont’d…
• Memory related instructions such as LDA, STA, MOV M,
LDAX, STAX, etc are used to transfer data between any CPU
register and I/O devices.
• Memory control signals MEMR & MEMW are used instead of
IOR & IOW, and the MP communicates with an I/o device as
if it were one of the memory locations.
Steps: in device selection & data transfer in memory-mapped
I/O:
1. Decode the whole 16 address lines to generate the device
address pulse.
2. AND the control signal with the device address pulse to
generate the device select (I/O select) pulse
3. Use the device select pulse to select the I/O port.
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 IO Mapped IO
• It treats them separately from memory.
– In this type of I/O, the P uses 8 address lines to
identify an input or output device.
– I/O devices are assigned a “port number” within the
8-bit address range of 00H to FFH.
– An address may refer either to a memory location or
to an I/O device. Thus, the P must issue another
signal on the IO/M line to differentiate b/n I/O and
memory; when IO/M=1, I/O device is selected,
otherwise memory is selected.

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 Cont’d…
− The user in this case would access these devices using the
IN & OUT instructions only.
− The P can identify 28 =256 input & 256 output devices
with address ranging from 00H to FFH.
− The P differentiates the input & output devices by the
control signals IOR & IOW respectively.
− The instructions IN & OUT are used for data transfer
between I/O devices and ACC.
IN portAdr8; input (read) data from an input device to
ACC,
OUT portAdr8; send (display) the contents of ACC to an
output device. 32
Steps:- in device selection and data transfer in peripheral-
mapped I/O:
1. The P places an 8-bit address on the address bus, which
is decoded by external decode logic.
2. The P sends a control signal IOR or IOW and enables
the I/O device
3. Data are transferred using the data bus between I/O and
ACC.

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 Memory Mapped IO Vs IO mapped IO
Memory Mapped IO
• IO is treated as memory.
• 16-bit addressing.
• More Decoder Hardware.
• Can address 216=64k
locations.
• Memory Instructions are
used.
• Memory control signals are
used.
• Data transfer b/w register
& IO.
IO Mapped IO
• IO is treated IO.
• 8- bit addressing.
• Less Decoder Hardware.
• Can address 28=256
locations.
• Special Instructions are
used like IN, OUT.
• Special control signals are
used.
• Data transfer b/w
accumulator & IO.
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 The interfacing of output devices
• Output devices are usually slow.
• Also, the output is usually expected to continue appearing on
the output device for a long period of time.
• Given that the data will only be present on the data lines for a
very short period (microseconds), it has to be latched externally.
• To do this the external latch should be enabled when the port’s
address is present on the address bus, the IO/M signal is set high
and WR is set low.
• The resulting signal would be active when the output device is
being accessed by the microprocessor.
• Decoding the address bus (for memory-mapped devices)
follows the same techniques discussed in interfacing memory.

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 Interfacing of Input Devices
• The basic concepts are similar to interfacing of output
devices.
• The address lines are decoded to generate a signal that is
active when the particular port is being accessed.
• An IORD signal is generated by combining the IO/M and
the RD signals from the microprocessor.
• A tri-state buffer is used to connect the input device to the
data bus.
• The control (Enable) for these buffers is connected to the
result of combining the address signal and the signal
IORD.
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