Engineering Project Summary (34)

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Our recent effort addressed
the increased testing time and lower product yield caused by
identifying an acceptable current sensing value in the current
mode dc to dc system.
As an integral part of the current mode dc to dc system, the
current sensing block influences the stability of a close loop and
contributes to the non-linearity of output voltage significantly.
However, the conventionally adopted current
sensing block varies with process, temperature and power
supply at a range of 10-30%. For instance, the inability to
adequately control the current sensing block might lead to
instability of the dc to dc system and adversely impact the unity
of a chip, leading to testing errors. Moreover, identifying an
acceptable current sensing value increases the testing time and
lowers the product yield, subsequently delaying delivery to
market and lowering market competitiveness.
(cont)
Therefore, we designed a sensing circuit that can
ensure proportionality of the current flowing through power mos, but
also can be modified according to the voltage value of the current.
A high speed and easily implemented
sensing circuit was analyzed under various loading currents and linear
variations with the loading current. The sensing value was then only
slightly altered less than during simulation with various temperatures.
Next, the value of variation in the sensing circuit was considered
acceptable during simulation with various process models.
According to our results, given various process models
and temperatures, the value of variation in the proposed sensing circuit
is lower than 1%. Additionally, the sensing value is linear with the
loading current. Importantly,
the proposed sensing circuit can facilitate the precise measurement of
the current in various sizes of power mos. Moreover, the sensing
circuit can be embedded in a chip without the need for an outer resistor,
as required by the conventional method. Such features can ensure that
its reliable application complies with consumer specifications.

Our group has
thoroughly explored the complexity of decelerating the rate
of rising retail costs of IC products.
Process variation has significantly abated
loss of product yield. However, given the
instability and inaccuracy of production equipment, fabs are
especially problematic in process control. Given the
constant role of process variation in manufacturing, a small
percentage of product yield loss occurs in manufacturing
ICs, ultimately increasing the retail
costs of IC products.
(cont)
Therefore, we developed an analysis method to
clarify the variation of process parameters and product yield rate are
related, e.g., resistors, using various resistor widths on a circuit layout.
Product yield rate was analyzed by placing
the product with various resistor widths on different wafers that were to
be manufactured in a fab. The yield rate of these wafers was then
monitored, with the optimal resistor width obtained when the wafer yield
rate is the highest. Our results indicated that the
proposed analysis method can enable the optimal resistor width to
reduce the influence on product yield rate when the resistors vary, thus
increasing product yield rate. By
varying the process parameters, the proposed method can analyze the
variation in product yield rate, thus decreasing the overhead
manufacturing costs and increasing market competitiveness. (NOTE :
Add 2-3 more sentences that describe more thoroughly how the
proposed method contributes to a particular field or sector)
Further details can be found at
http://www.chineseowl.idv.tw