FinFETs: From Circuit to

Architecture
Niraj K. Jha
Dept. of Electrical Engineering
Princeton University

Joint work with: Anish Muttreja, Prateek Mishra,

Chun-Yi Lee, Ajay Bhoj and Wei Zhang
Talk Outline
• Background
• Low Power FinFET Circuits
– Unusual Logic Styles
– Unusual Dual-Vdd /Dual-Vth Circuits
• Architectural Impact
• Other Ongoing Work
• Conclusions
 Why Double-gate Transistors ?
Feature size 32 nm 10 nm
Bulk CMOS DG-FETs
Gap Non-Si nano devices

• DG-FETs can be used to fill this gap

• DG-FETs are extensions of CMOS
– Manufacturing processes similar to CMOS
• Key limitations of CMOS scaling addressed through
– Better control of channel from transistor gates
– Reduced short-channel effects
– Better Ion/Ioff
– Improved sub-threshold slope
– No discrete dopant fluctuations
What are FinFETs?
• Fin-type DG-FET
– A FinFET is like a FET, but the channel has been “turned on its edge”
and made to stand up

Si Fin
Independent-gate FinFETs
Oxide insulation
Back Gate

• Both the gates of a FET can be independently controlled

• Independent control
– Requires an extra process step
– Leads to a number of interesting analog and digital circuit
structures
 FinFET Width Quantization

• Electrical width of a FinFET

with n fins: W = 2*n*h
• Channel width in a FinFET is
quantized
• Width quantization is a
design challenge if fine
control of transistor drive
strength is needed
– E.g., in ensuring FinFET structure
stability of memory Ananthan, ISQED’05
cells
Talk Outline
• Background
• Low Power FinFET Circuits
– Unusual Logic Styles
– Unusual Dual-Vdd /Dual-Vth Circuits
• Architectural Impact
• Other Ongoing Work
• Conclusions
Motivation: Power Consumption
• Traditional view of CMOS power consumption
– Active mode: Dynamic power (switching + short
circuit + glitching)
– Standby mode: Leakage power
• Problem: rising active leakage
– 40% of total active mode power consumption (70nm
bulk CMOS) †

†J. Kao, S. Narendra and A. Chandrakasan, “Subthreshold leakage modeling and reduction
techniques,” in Proc. ICCAD, 2002.
Logic Styles: NAND Gates

SG-mode NAND IG-mode NAND

IG-mode
pull up
pull up bias
voltage

LP-mode NAND IG/LP-mode NAND

pull down LP-mode
bias voltage pull down
Comparing Logic Styles
Design Mode Advantages Disadvantages
SG Fastest under all load High leakage† (1μA)
conditions
LP Very low leakage (85nA), Slowest, especially under
low switched capacitance load. Area overhead (routing)

IG Low area and switched Unmatched pull-up and

capacitance pull-down delays.
High leakage (772nA)
IG/LP Low leakage (337nA), Almost as slow as LP mode
area and switched
capacitance
†
Average leakage current for two-input NAND gate (Vdd = 1.0V)
 FinFET Circuit Power Optimization
• Construct FinFET-based
32 nm PTM
FinFET models Logic
Logicgate
gate Synopsys technology libraries
inFET
FinFET models
models
(UFDG, PTM) designs
designs • Extend linear programming
based cell selection† for FinFETs
Delay/power • Use optimized netlists to
characterization compare logic styles at a range
in Benchmark
of delay constraints
SPICE

Minimum-delay
synthesis in SG-mode
IG SG
netlist
Design
Synopsys libraries
Compiler
Power-optimized
IG/LP LP
mixed-mode netlists
Linear
programming SG+ SG+LP
†D. Chinnery and K. Keutzer, based cell IG/LP SG+IG
“Linear programming for sizing, Vdd selection
and Vt assignment,” in Proc.
ISLPED, 2005.
 Power Consumption of Optimized Circuits

Estimated total power

consumption for
ISCAS’85 benchmarks
Vdd = 1.0V, α = 0.1, 32nm
FinFETs

Available modes

Total power savings Leakage power savings

• 110% arrival time (a.t.) (34%) • 110% a.t. (68.5%)
• 120% a.t. ( 47.5%) • 120% a.t. (80.3%)
Talk Outline
• Background
• Low Power FinFET Circuits
– Unusual Logic Styles
– Unusual Dual-Vdd /Dual-Vth Circuits
• Architectural Impact
• Other Ongoing Work
• Conclusions
 Dual-Vdd FinFET Circuits

• Conventional low- Reverse bias Higher Vth

Vgs =+0.08V
power principle:
1.08V 1V
– 1.0V Vdd for critical logic, Leakage
0.7V for off-critical paths current
Vin
• Our proposal:
overdriven gates
– Overdriven FinFET gates
leak a lot less! Overdriven
inverter
Vth Control with Multiple Vdd ’s (TCMS)
• Using only two Vdd ’s saves leakage only in P-type FinFETs, but
not in N-type FinFETs
• Solution
– Use a negative ground voltage (V ss ) to symmetrically save leakage in
H

N-type FinFETs
–
–

Vdd H Vdd L

Symmetric
Vdd H 1.08V threshold control
for P and N
Vdd L 1.0V
Vss H -0.08V
TCMS buffer
Vss L
0.0V Vss H Vss L
Exploratory Buffer Design
VHdd VLdd VHdd VLdd

i’
i
S1 S2 lopt S1 S2

VHss VLss VHss VLss

• Size of high-Vdd inverters kept small to minimize leakage in
them
• Wire capacitances not driven by high-Vdd inverters
• Output inverter in each buffer overdriven and its size (and
switched capacitance) can be reduced
 Power Savings
Power Savings
component
Dynamic -29.8%
power
Leakage 57.9%
power
Total power 50.4%

• Benchmarks are nets extracted from real layouts and scaled to 32nm
http://dropzone.tamu.edu/~zhouli/GSRC/fast_buffer_insertion.html
Fin-count Savings

• Transistor area is measured as the total number of fins

required by all buffers
• TCMS can save 9% in transistor area
TCMS Extension
e nor10011
e
b X2 X1 nor11011
b
X1 X1
inv101
d d
X8 X2
X2 X1

nor01100
X8 X2

inv101

nand01001
inv101
c b X2 c b X1
X16 X2
d inv101 d nor00111
X8 X4 nor10011 nand00110
X16 X8
X4 X4 X2 X1
inv101 nor01100
a a
X16 X8
X8 X2

X16 X8

Level: 1 2 3 4 inv101

Level : 1 2 3 4

Delay-minimized netlist Power-optimized netlist

Power : 283.6uW Power : 149.9uW
Area: 538 fins Area: 216 fins
Power Reduction (ISCAS’85 Benchmarks)

% reduction in power

90

80

70
% reduction in power

60

50

40

30

20

10

0
110% 130% 150% 170% 190%
ATCs
 Power-minimized vs Delay-
minimized Netlists at 130% ATC
TCMS TCMS (Single- Dual-Vdd
Vth

% reduction in
dynamic power
53.3 49.8 51.4
% reduction in
leakage power
95.8 95.7 95.8
% reduction in
total power
67.6 65.3 66.3
% reduction in
Fin-count
65.2 59.5 61.6
Talk Outline
• Background
• Low Power FinFET Circuits
– Unusual Logic Styles
– Unusual Dual-Vdd /Dual-Vth Circuits
• Architectural Impact
• Other Ongoing Work
• Conclusions
Orion-FinFET
• Extends ORION for FinFET-based power
simulation for interconnection networks
• FinFET power libraries for various
temperatures and technologies nodes
• Power breakdown of interconnection
networks for different FinFET modes
• Power comparison for different FinFET
modes under different traffic patterns
Router Microarchitecture & Pipeline Stages

VC allocation
arbiters

Req
Input buffers
From source
RC ……
.
From north
RC ……
.
Route
From south
RC
VC ……
Sw itch
calculation allocation. allocation
Power Simulation Flow
F in
mo d e
Run UFDG
S P IC Esim u la tio n
L o g ic-le v e l
ro u te r c irc u its F in F E Tlo
c h a ra c
F in c o u n t s p e c ific a tio n
fo r ol g ic g a te s C a p a c ita n c ele &a k a g e
ex tra c tio n
R o u te r tra ffic R o u te r F in F E
p ro file p ow e r m odel lib r
Power Breakdown for SG/LP Modes
• 4X4 mesh network: 5 ports/router, 48-flit buffer/port
• Flit width = 128 bits
• Clock frequency = 1GHz
0.03 0.7

0.025 0.6

0.5
0.02
0.4

Watt
Watt

0.015
0.3
0.01
0.2
0.005 0.1

0 0
SG LP 1.2/-0.2 LP 1.4/-0.4 SG LP 1.2/-0.2 LP1.4/-0.4

B uffer C rossba r A rbiter C lock Leakage Router Link Clk dist Driver leak

Router power breakdown Network power breakdown

Bulk CMOS vs. LP-mode FinFETs
• Bulk CMOS simulation: 32nm predictive
technology model
• Leakage power of bulk CMOS network 2.68X as
compared to an LP-mode FinFET network
4
3.5
3
2.5
Watts

2
1.5
1
0.5
0
Bulk CMOS LP mode (1.2/-0.2)

Router Dynamic Link Clk dist Leakage

Router Leakage Power vs. Temp.
• Leakage power of SG-mode router grows
much faster with temp. than for LP-mode
• Leakage power ratio at 105oC: 7:1
0.014

0.012
SG
LP 1.2/-0.2
Leakage power (Watt)

0.01

0.008

0.006

0.004

0.002

0
25 35 45 55 65 75 85 95 105
Temperature
Talk Outline
• Background
• Low Power FinFET Circuits
– Unusual Logic Styles
– Unusual Dual-Vdd /Dual-Vth Circuits
• Architectural Impact
• Other ongoing work
• Conclusions
FinFET SRAM and Embedded DRAM
Design
• FinE: Two-tier FinFET simulation framework for
FinFET circuit design space exploration:
– Sentaurus TCAD+UFDG SPICE model
– Quasi Monte-Carlo simulation for process variation analysis
– Thermal analysis using ThermalScope
– Yield estimation
• Variation-tolerant ultra low-leakage FinFET SRAMs at
lower technology nodes
• Gated-diode FinFET embedded DRAMs
Extension of CACTI for FinFETs
• Selection of any of the FinFET SRAM and
embedded DRAM cells
• Use of any of the FinFET operating modes
• Scaling of FinFET designs from 32nm to 22nm,
16nm and 10nm technology nodes
• Accurately modeling the behavior of a wide
range of cache configurations
FPGA vs. ASICs
• Distributed non-volatile nano RAMs: main
storage for reconfiguration bits
CMOS fabrication Nano RAM
compatible on-chip storage • Fine-grain reconfiguration (even cycle-by-
cycle) and logic folding
 More than an order of magnitude increase in logic
density and area-delay product
 Competitive performance and moderate power
Run-time Temporal consumption
reconfiguration NATURE logic folding  Non-volatility: useful in low power & secure
processing
• NanoMap to map application to NATURE
 Significant area-delay trade-off flexibility

Design Logic
flexibility density
Conclusions
• FinFETs a necessary semiconductor evolution step
because of bulk CMOS scaling problems beyond 32nm
• Use of the FinFET back gate leads to very interesting
design opportunities
• Rich diversity of design styles, made possible by
independent control of FinFET gates, can be used
effectively to reduce total active power consumption
• TCMS able to reduce both delay and subthreshold
leakage current in a logic circuit simultaneously
• Time has arrived to start exploring the architectural
trade-offs made possible by switch to FinFETs