Writing Problem and Hypothesis

Statements for Engineering Research(1)

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Setting of work proposal :
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Work problem :
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Quantitative specification of problem :

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Importance of problem :
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Project need : ,
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Work objective : ?
Methodology to achieve objective
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Anticipated results :
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Contribution to field :
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()
Consumer demand for hard disc bandwidth has
significantly increased in recent years owing to the large size of
files and increased disc size. However, the
conventional interface for hard discs cannot easily support such
a high bandwidth and demands many pin counts to comply with
such a requirement. (NOTE : Add 3-4 sentences that describe
characteristics of the problem or statistics that reflect its severity)
For instance, the conventional interface
requires 28 pins and can only support 133 MHz bandwidth.
Consequently, the failure rate in manufacturing exceeds 5%
when the conventional interface must satisfy 150 MHz bandwidth
requirements. Doing so prevents the
integration of many functions into a chip with limited pin counts
because the conventional interface not only requires many pins,
but also makes commercialization impossible.
Therefore, a novel connecting interface for hard discs must be
developed, capable of supporting up to 150 MHz bandwidth
requirements and minimizing the number of pins to four.
()
A novel connecting interface can be
developed for hard discs for supporting up to 150 MHz
bandwidth requirements and minimizing the number of pins
to four. To do so, this novel connecting
interface with serial transmitting and receiving lines can be
used to facilitate communication between the system and
hard disc. The serial interfaces can then be used to
eliminate the cross talk between transmitted and received
data, discovered in conventional interfaces, and can easily
support bandwidths of up to 150 MHz. Next, the minimal
pin requirement can be satisfied using the serial interfaces.
()
As anticipated, the novel serial interface can
facilitate robust communication between system and hard
disc and easily support up to 150 MHz bandwidth
requirements. Moreover, the proposed
interface can allow chipset vendors to integrate more
functions into one chip than they did before. In addition to
making a high performance hard disc commercially feasible,
the proposed interface can be easily upgraded in the future.
(NOTE : Add 2-3 more sentences that describe more
thoroughly how the proposed method contributes to a
particular field or sector)
()
In high-speed optical communications, the clock
and data recovery (CDR) circuit is largely responsible for
recovery of the clock used to sample the data bits. The signal
stream in point-to-point communication systems such as SONET
is continuous; otherwise, during the idle time, some
synchronization bits are transmitted to maintain the bit-level
synchronization between the transmitter and the receiver. In
these systems, CDR based on Phase Lock Loop (PLL) design is
widely recognized as the optimal solution. PLL-based CDR has
been increasingly studied to remain apace of higher data rate
system requirements. Time division multiplexing (TDM) passive
optical network (PON) is a promising means of resolving
bottlenecks in broadband access. Among the standards
specified and the most widely accepted ones include Ethernet
PON and Gigabit PON standardized by IEEE and ITUT-T,
respectively. In these TDM PON systems, the upstream traffic
aggregating to the optical line terminal consists of bursts from
various optical network units.
()
Therefore, recovering a clock in a relatively
short time to increase efficiency is problematic given that
the burst length in conventional PON systems is no longer
than thousands of bits. Applying the conventionally adopted
PLL CDR to PON systems is problematic given its relatively
long recovery time. (NOTE : Add 2-3 sentences that
describe characteristics of the problem or statistics that
reflect its severity) For instance, a
commercially available PLL-CDR chip used in a legacy
continuous optical link generally takes two thousand bits to
lock its voltage controlled oscillator (VCO) to the incoming
data in both phase and frequency.
This long locking time appears to be intolerable for systems
like PON. Therefore, a novel CDR scheme
must be developed, capable of recovering a clock
efficiently to increase the pocket efficiency of PON systems.
()
A novel CDR scheme can be designed,
capable of recovering a clock efficiently to increase the
pocket efficiency of PON systems. To do
so, a hybrid phase and delay lock loop architecture can be
derived, consisting of a VCO, voltage controlled delay line,
phase detector, charge pump and low pass filter. HSPICE
can then be simulated. Next, a prototype can be designed
to demonstrate the effectiveness of the CDR scheme.
As anticipated, the proposed monolithic scheme
can acquire the sampling phase well within 50 ns in a 2.5
Gbps system such as PON. In addition to
averting frequency jittering greater than 6MHz, i.e.
4800ppm, the proposed CDR scheme can facilitate a more
aggressive design, with an even lower loop gain. (NOTE :
Add 2-3 more sentences that describe more thoroughly
how the proposed method contributes to a particular field or
sector)
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