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MOCHI BALARAJU
R.NO. 707
I/IV M.TECH VLSI
CMR INSTITUTE OF TECHNOLOGY
MALLESHGADA@GMAIL.COM
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| FIR filter is the foundational element of DSP systems.

| Due to the advantages of versatility, flexibility, large scale of FPGA,

a number of applications in digital system designing based on FPGA
have been developed for telecommunications, controlling and
information processing system.
| Typical FIR filters based on FPGA could be mainly classified into two
types of structures that are
- bit-serial model
-bit-parallel model.
| In this, a digital-serial algorithm module is used in bit-serial FIR
filter in order to avoid the disadvantages of low speed in the bit-
serial algorithm module and high hardware consumption in the bit-
parallel algorithm module
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ñ In a digital-serial algorithm, the W bits of a data word are processed

in units of the digit-size N in P clock cycles that is equal to W/N.
ñ Cycle P is called as sampling cycle. So digital-serial algorithm
possess of the advantages of bit-serial algorithm and bit-parallel
algorithm

ñ The foundational function module in the most of the digital signal

processor includes adder, complementary and delay circuit, which
realize more complex structures such as multiplier, accumulator and
so on.
ñ According to digital-serial algorithm, we construct digital-serial FIR
filter architecture based on these foundational modules.
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ñ A basic element in the implementation of a

digital-serial algorithm is the digital-serial
adder, .
ñ Digital-serial adder is a circuit with a
previous carry that adds two digits along.
ñ The addition carry out N bit at one time and
the carry are delivered from one full-adder to
the next one. When the next output data
arrives, the carry output of the digital-serial
adder feedbacks to the first full adder in the
next clock cycle.
Digital serial adder

# 2- full-adders with carry

# 3-D trigger
- and the output of the circuit are the sum and a
new carry
# Two operating numbers, A and B, deliver one data to the digital-
serial adder at one time.
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# Multipliers are essential components in many DSP
applications.
# One digital-serial multiplier with fixed correlated
modulus could be accomplished by a structure of
synthetic digital-serial multiplier.
# The structure of multiplier with N=2 is
ñ In this, X is a digital-serial input of the multiplier,
ñ Y is a parallel input of the multiplier,
ñ PI is an output product of the front multiplier.
ñ X· is a shift output, PO is a digital-serial output.
ñ Digital-serial input and parallel input produce each product through
2-input and gate .
ñ Every product added to the output product PI of the front multiplier
module, and then the final output is got by PO.
ñ In this way, each digital-serial multiplier module could be tightly
connected to realize a good assembly line operating and the
throughput of the digital-serial multiplier is added.
ñ As in Fig3b, the structure of the multiplier uses the assembly line
operating, and S is the digital-serial output.


| In FIR filters, delay element means that

the whole data word is delayed. The delay
is used to proofread data word and to
control synchronous signals correct, which
can be implemented by proper shift
register length.
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ñ The structure of digital-serial FIR filter

ñ FIR filter algorithm is dispersing convolution of input signals that have one
group of correlate modulus. The transfer function of M steps FIR filter can
be expressed as

ñ According to this equation, the transform function can be implemented with

digital-serial multiplier, delay element and digital-serial adder.
ñ Fig 4 (a) shows the flow graph of signal in inversion FIR filter. Usually, one
FIR filter with M steps needs M multipliers and M-1 adders.
ñ According to the signal flow graph of the digital-serial FIR filter, digital-serial
processing unit is implemented with the unit of digital-serial FIR filter in
digital-serial algorithm by corresponding foundational function module.
Digital-serial processing unit is shown in Fig 4 (b). FIR filter with M steps
consists of M digit-serial processing unit.
 ñFig 4 (a) shows the flow graph of signal in inversion
FIR filter. Usually, one FIR filter with M steps needs M
multipliers and M-1 adders.
ñAccording to the signal flow graph of the digital-serial
FIR filter, digital-serial processing unit is implemented
with the unit of digital-serial FIR filter in digital-serial
algorithm by corresponding foundational function
module.

Digital-serial processing unit is shown in Fig 4 (b). FIR filter with M steps consists
of M digit-serial processing unit.
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ñ Very high-speed integrated circuit (VHSIC) hardware description

language (VHDL) is a kind of language for describing VHSIC in IEEE
standards. Finally, VHDL is easy to understand and transplants that
the renewing system could be realized just by adjusting software.
ñ Considering the advantages of VHDL, we choose it to describe
digital-serial FIR filters and chip named Xilinx XC4010 are used to
implement required digital-serial FIR filters.
ñ The main technical parameters of XC4010 are:
ñ 160 maximum usable i/o pins
ñ 400 carry logic builts (CLBs)
ñ 13000 RAM bits
ñ 1.2mA output drive current
ñ Digital-serial FIR filters with N=4 are faster
than the digital-serial FIR filters with N=2,
but consume more area.
ñ The area-time product of unsigned digital-
serial FIR filters with N=2 is 14%, lower than
that of bit-serial FIR filters, 4.4% lower than
the digital-serial FIR filters with N=4 and the
signed are 19% and 24%.
ñ The function of digital-serial FIR filters with
N=2 is better than that of traditional bit-
serial manner in speed and hardware
utilization.
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ñ In this paper, a basic digital-serial algorithm is presented and

the design of digital-serial FIR filter is proposed according to
the digital-serial algorithm.
ñ The digital ²serial FIR filter with 5 steps is designed with
VHDL and implemented with FPGA. The results demonstrate
that this structure can save hardware resources as the
module with digital-serial algorithm does and process
information in high speed as module with bit-serial algorithm
does.
ñ Compared with the corresponding bit-serial FIR filters, this
digital-serial FIR filter is better than traditional bit-serial
manner in processing speed and hardware consumption.
 

1] V. Tarokh, H. Jafarkhani, and A. R.

Calderbank, IEEE FIR Filters Based Theory, vol.
45, no. 5, Jul 1999, pp. 1456²67

THANQ YOU.