CSE477

VLSI Digital Circuits

Fall 2002

Lecture 17: Static Sequential

Circuits
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg477

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

CSE477 L17 Static Sequential Logic.1 Irwin&Vijay, PSU, 2002

 Review: How to Choose a Logic Style
 Must consider ease of design, robustness (noise immunity),
area, speed, power, system clocking requirements, fan-out,
functionality, ease of testing
4-input NAND
Style # Trans Ease Ratioed? Delay Power
Comp Static 8 1 no 3 1
CPL* 12 + 2 2 no 4 3
domino 6+2 4 no 2 2 + clk
DCVSL* 10 3 yes 1 4
* Dual Rail

 Current trend is towards an increased use of

complementary static CMOS: design support through DA
tools, robust, more amenable to voltage scaling.

CSE477 L17 Static Sequential Logic.2 Irwin&Vijay, PSU, 2002

 A time was probably coming when components would
operate so quickly that the distance that signals had to
travel would intimately affect the speed of most
commercial computers. Then miniaturization and speed
would become more nearly synonymous.
The Soul of a New Machine, Kidder, pg. 160

CSE477 L17 Static Sequential Logic.3 Irwin&Vijay, PSU, 2002

 Sequential Logic

Inputs Outputs
Combinational
Logic

Current Next

Registers
State State State

clock

CSE477 L17 Static Sequential Logic.4 Irwin&Vijay, PSU, 2002

 Timing Metrics
In D Q Out

clock
clock

tsu thold time

In data
stable
tc-q time

Out output output

stable stable
time
CSE477 L17 Static Sequential Logic.5 Irwin&Vijay, PSU, 2002
 System Timing Constraints

Inputs Outputs
Combinational
Logic

Current Next

Registers
State State

State
T (clock period)
clock

tcdreg + tcdlogic ≥ thold T ≥ tc-q + tplogic + tsu

CSE477 L17 Static Sequential Logic.6 Irwin&Vijay, PSU, 2002

 Static vs Dynamic Storage

 Static storage
● preserve state as long as the power is on
● have positive feedback (regeneration) with an internal connection
between the output and the input
● useful when updates are infrequent (clock gating)

 Dynamic storage
● store state on parasitic capacitors
● only hold state for short periods of time (milliseconds)
● require periodic refresh
● usually simpler, so higher speed and lower power

CSE477 L17 Static Sequential Logic.7 Irwin&Vijay, PSU, 2002

 Latches vs Flipflops

 Latches
● level sensitive circuit that passes inputs to Q when the clock is
high (or low) - transparent mode
● input sampled on the falling edge of the clock is held stable
when clock is low (or high) - hold mode

 Flipflops (edge-triggered)
● edge sensitive circuits that sample the inputs on a clock
transition
- positive edge-triggered: 0 → 1
- negative edge-triggered: 1 → 0
● built using latches (e.g., master-slave flipflops)

CSE477 L17 Static Sequential Logic.8 Irwin&Vijay, PSU, 2002

 Review: The Regenerative Property
Vi1 Vo1 Vi2 Vo2

cascaded inverters
Vi2 = Vo1

A If the gain in the transient

region is larger than 1,
C
only A and B are stable
operation points. C is a
metastable operation
B point.
Vi1 = Vo2

CSE477 L17 Static Sequential Logic.9 Irwin&Vijay, PSU, 2002

 Bistable Circuits
 The cross-coupling of two Vi1
inverters results in a bistable
circuit (a circuit with two Vi2
stable states)
 Have to be able to change the stored value by making A
(or B) temporarily unstable by increasing the loop gain to
a value larger than 1
● done by applying a trigger pulse at Vi1 or Vi2
● the width of the trigger pulse need be only a little larger than the
total propagation delay around the loop circuit (twice the delay of
an inverter)

 Two approaches used

● cutting the feedback loop (mux based latch)
● overpowering the feedback loop (as used in SRAMs)

CSE477 L17 Static Sequential Logic.10 Irwin&Vijay, PSU, 2002

 Review (from CSE 271): SR Latch

S R Q !Q
S 0 0 Q !Q memory
!Q
1 0 1 0 set

0 1 0 1 reset
Q
R 1 1 0 0 disallowed

CSE477 L17 Static Sequential Logic.11 Irwin&Vijay, PSU, 2002

 Review (from CSE 271): Clocked D Latch

D
!Q

D Latch
Q
D Q

clock

transparent mode clock

clock

hold mode
CSE477 L17 Static Sequential Logic.12 Irwin&Vijay, PSU, 2002
 MUX Based Latches
 Change the stored value by cutting the feedback loop

feedback feedback

1 0
Q Q
D 0 D 1

clk clk

Negative Latch Positive Latch

Q = clk & Q | !clk & D Q = !clk & Q | clk & D

transparent when the transparent when the
clock is low clock is high

CSE477 L17 Static Sequential Logic.13 Irwin&Vijay, PSU, 2002

 TG MUX Based Latch Implementation

clk

!clk

input sampled
D (transparent mode)

clk
clk
D Latch

D Q
!clk

clk feedback
(hold mode)
CSE477 L17 Static Sequential Logic.14 Irwin&Vijay, PSU, 2002
 PT MUX Based Latch Implementation

clk !Q

D Q

input sampled
(transparent mode)
!clk
 Reduced clock load, but
clk
threshold drop at output
of pass transistors so !clk
reduced noise margins
and performance
feedback
(hold mode)
CSE477 L17 Static Sequential Logic.15 Irwin&Vijay, PSU, 2002
 Latch Race Problem

Combinational
Logic B
B B’

Registers clk
State

Which value of B is stored?

clk

Two-sided clock constraint

T ≥ tc-q + tplogic + tsu

Thigh < tc-q + tcdlogic

CSE477 L17 Static Sequential Logic.16 Irwin&Vijay, PSU, 2002

 Master Slave Based ET Flipflop

D FF
D Q

0
1 Q clock
1
QM
D 0
clk clk
clk
Slave D
Master

clk = 0 transparent hold QM

clk = 0→1 hold transparent Q

CSE477 L17 Static Sequential Logic.17 Irwin&Vijay, PSU, 2002

 MS ET Implementation
Master Slave

I2 T2 I3 I5 T4 I6 Q
QM

I1 T1 I4 T3
D

clk

clk

!clk

CSE477 L17 Static Sequential Logic.18 Irwin&Vijay, PSU, 2002

 MS ET Implementation
Master Slave

I2 T2 I3 I5 T4 I6 Q
QM

I1 T1 I4 T3
D

clk

master transparent master hold

slave hold slave transparent
clk

!clk

CSE477 L17 Static Sequential Logic.19 Irwin&Vijay, PSU, 2002

 MS ET Timing Properties

 Assume propagation delays are tpd_inv and tpd_tx , that the

contamination delay is 0, and that the inverter delay to
derive !clk is 0
 Set-up time - time before rising edge of clk that D must be
valid

 Propagation delay - time for QM to reach Q

 Hold time - time D must be stable after rising edge of clk -

CSE477 L17 Static Sequential Logic.20 Irwin&Vijay, PSU, 2002

 MS ET Timing Properties

 Assume propagation delays are tpd_inv and tpd_tx , that the

contamination delay is 0, and that the inverter delay to
derive !clk is 0
 Set-up time - time before rising edge of clk that D must be
valid
3 * tpd_inv + tpd_tx

 Propagation delay - time for QM to reach Q

tpd_inv + tpd_tx
 Hold time - time D must be stable after rising edge of clk

zero

CSE477 L17 Static Sequential Logic.21 Irwin&Vijay, PSU, 2002

 Set-up Time Simulation

3
Q
2 .5

2 tsetup = 0.21 ns
QM
1 .5
Volts

1 D clk
0 .5
I2 out
0

-0 .5 works correctly
0 0 .2 0 .4 0 .6 0 .8 1
Time (ns)

CSE477 L17 Static Sequential Logic.22 Irwin&Vijay, PSU, 2002

 Set-up Time Simulation

3
Q
2 .5
I2 out tsetup = 0.20 ns
2

1 .5
Volts

1
D clk
0 .5

0 QM

- 0 .5 fails
0 0 .2 0 .4 0 .6 0 .8 1
Time (ns)

CSE477 L17 Static Sequential Logic.23 Irwin&Vijay, PSU, 2002

 Propagation Delay Simulation

2 .5

2 tc-q(LH) = 160 psec

1 .5
Volts

1 tc-q(LH) tc-q(HL) = 180 psec

tc-q(HL)
0 .5

-0 .5
0 0 .5 1 1 .5 2 2 .5
Time (ns)

CSE477 L17 Static Sequential Logic.24 Irwin&Vijay, PSU, 2002

 Reduced Load MS ET FF
 Clock load per register is important since it directly
impacts the power dissipation of the clock network.
 Can reduce the clock load (at the cost of robustness) by
making the circuit ratioed

clk !clk
I1 I3
QM
D T1 T2 Q

I2 I4
!clk clk
reverse conduction

● to switch the state of the master, T1 must be sized to overpower I2

● to avoid reverse conduction, I4 must be weaker than I1

CSE477 L17 Static Sequential Logic.25 Irwin&Vijay, PSU, 2002

 Non-Ideal Clocks

clk clk

!clk !clk

Ideal clocks Non-ideal clocks

clock skew

1-1 overlap

0-0 overlap

CSE477 L17 Static Sequential Logic.26 Irwin&Vijay, PSU, 2002

 Example of Clock Skew Problems
X !clk Q
clk

P1 A P3 I3 I4 !Q
D I1 I2

B
P2 P4

!clk clk

Race condition – direct path from D to Q during the short

time when both clk and !clk are high (1-1 overlap)
Undefined state – both B and D are driving A when clk
and !clk are both high
Dynamic storage – when clk and !clk are both low (0-0
overlap)
CSE477 L17 Static Sequential Logic.27 Irwin&Vijay, PSU, 2002
 Pseudostatic Two-Phase ET FF
X clk2 Q
clk1

P1 A P3 I3 I4 !Q
D I1 I2

B
P2 P4

clk2 clk1
dynamic
master transparent storage
slave hold

clk1 master hold

tnon_overlap slave transparent
clk2

CSE477 L17 Static Sequential Logic.28 Irwin&Vijay, PSU, 2002

 Two Phase Clock Generator
A clk1

clk

B clk2

clk

clk1

clk2

CSE477 L17 Static Sequential Logic.29 Irwin&Vijay, PSU, 2002

 Power PC Flipflop
clk !clk

1D Q 0
0 1 1

!clk clk

clk

!clk
CSE477 L17 Static Sequential Logic.30 Irwin&Vijay, PSU, 2002
 Power PC Flipflop
clk !clk

1D Q 0 →1
0 →1 1 →0 1 →0

!clk clk

master transparent master hold

slave hold slave transparent
clk

!clk
CSE477 L17 Static Sequential Logic.31 Irwin&Vijay, PSU, 2002
 Ratioed CMOS Clocked SR Latch

off on
M2 M4
Q 1
0 !Q

clk M6 M8 clk
M1 M3
on off
M7 R1
0 S M5
off on

CSE477 L17 Static Sequential Logic.32 Irwin&Vijay, PSU, 2002

 Ratioed CMOS Clocked SR Latch

off → on on → off
M2 M4
Q 1 →0
1← 0 !Q
off->on off->on
0 → 1 clk M6 M8 clk 0 → 1
M1 M3
on → off off → on
M7 R1
0 S M5
off on

CSE477 L17 Static Sequential Logic.33 Irwin&Vijay, PSU, 2002

 Sizing Issues

1.5
so W/L5and6 > 3
!Q (Volts)

0.5

0
2 2.5 3 3.5 4
W/L5and6
W/L2and4 = 1.5µ m/0.25 µ m
W/L1and3 = 0.5µ m/0.25 µ m
CSE477 L17 Static Sequential Logic.34 Irwin&Vijay, PSU, 2002
 Transient Response

SET

2
Q & !Q (Volts)

!Q
Q
1 tc-!Q tc-Q

0
0.9 1 1.1 1.2 1.3 1.4 1.5
Time (ns)

CSE477 L17 Static Sequential Logic.35 Irwin&Vijay, PSU, 2002

 6 Transistor CMOS SR Latch

clk clk

R S

clk
clk M2 M4
Q M6 S
M5 !Q
R

M1 M3

CSE477 L17 Static Sequential Logic.36 Irwin&Vijay, PSU, 2002

 Next Lecture and Reminders
 Next lecture
● Dynamic sequential circuits
- Reading assignment – Rabaey, et al, 7.3, 7.7

 Reminders
● Project prototypes due today
● Project final reports due December 5th
● HW4 due November 5th
● HW5 out November 5th and due November 19th
● Final exam scheduled
- Monday, December 16th from 10:10 to noon in TBD

CSE477 L17 Static Sequential Logic.37 Irwin&Vijay, PSU, 2002