Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Spring 2011

Data Converters Switched-Capacitor Circuits
Professor Y. Chiu
EECT 7327
Spring 2011
Switched-Capacitor Circuits
–1–
Professor Y. Chiu
EECT 7327
Continuous-Time Integrator
Spring 2011
t
C2 1
vo  t     v    d
in
R1
R1  C2 
Vi Vo  1  1
Vo
H  s   s    
Vi 
 1 2 s
R C
   R1  C2
C2
Goal: Vi SC
Vo
Approach: emulating resistors with switched capacitors
–2–
Professor Y. Chiu
EECT 7327
Concept of Switched Capacitor

Spring 2011
Ф2 C Ф2 Non-overlapping
R VA VB two-phase clock
VA VB
Ф1 <i> Ф1
i
Ф1
1 q C
i  V A  VB  i   VA  VB  Ф2
R T T
T T C
 Req  so,   Req ,1  C2 
C1
 C2  T  2
C1
C
• A switched capacitor is a discrete-time “resistor”

• RC time constant set by capacitor ratio C2/C1 (match considerably better
than R and C) and clock period T (flexibility)
–3–
Professor Y. Chiu
EECT 7327
Switched Capacitors
Spring 2011
Shunt-type Series-type 2-phase clock
Ф1 Ф2 Ф1 C
VA VB VA VB
Ф1 Ф2 Ф1 Ф2 Ф1 Ф2
C Ф2
Ф2(Ф1) C Ф2
VA VB
Stray-insensitive
Ф1(Ф2) Ф1
• Shunt- and series-type SCs are simple and cheap to implement

• Stray-insensitive SC requires 2 more switches, what’s the advantage
besides being more flexible (i.e., w/ or w/o the T/2 delay)?
–4–
Professor Y. Chiu
EECT 7327
Discrete-Time Integrator (DTI)

Spring 2011
Shunt-type Series-type
C2
Ф2 C2
Ф1 Ф2
Ф1 C1
Vi
Vo Vi
Vo
C1
2-phase clock
Ф1 Ф2 Ф1 Ф2 Ф1 Ф2
What are the VTFs (z-domain) of these DTIs, assuming no parasitic

capacitance is present?
–5–
Professor Y. Chiu
EECT 7327
Shunt-Type DTI
Spring 2011
T
Ф1 C2
(sample) Ф1 Ф2 Ф1 Ф2 Ф1 Ф2
Vi
Vo
vi(t)

C1 (n-1)
(n)
0 t
(n+1)
Ф2 C2
(update)
vo(t) (n+1)
(n)
Vi
Vo 0 t
C1 (n-1)
Charge conservation law (ideal):

Total charge on C1 and C2 during Ф1→ Ф2 transition must remain unchanged!
–6–
Professor Y. Chiu
EECT 7327
Shunt-Type DTI
Spring 2011
Ф1 Ф2
(sample) C2 (update) C2
Vi
C1
Vo  Vi
C1
Vo
 Q    V  n   C
1 i 1  Vo  n   C2  Q    0  C
2 1  Vo  n  1  C2
 Q     Q   
1 2  Vi  n   C1  Vo  n   C2  0  C1  Vo  n  1  C2
Vi  z   C1  Vo  z   C2   z  Vo  z   C2
Vo  z  C1 z 1 C1 z 1/2
H  z   or 
Vi  z  C2 1  z 1 C 2 1  z 1
–7–
Professor Y. Chiu
EECT 7327
Series-Type DTI
Spring 2011
Ф1 Ф2 Ф1 Ф2 Ф1 Ф2 Ф1 Ф2
(sample/update)  (reset C1)
vi(t)
(n-1)
(n)
0 t
Ф2 C2
(n+1)
Ф1 C1
Vi vo(t) (n)
Vo
(n-1)
0 t
(n+1)
Vo  z  C 1
VTF: H  z   1
Vi  z  C2 1  z 1
–8–
Professor Y. Chiu
EECT 7327
Stray Capacitance
Spring 2011
Shunt-type Series-type
Ф2
C2
Ф1 Ф2 C2
Ф1
A
C1
Vi
Vo Vi
C1 A Vo
C2
4
C1 • Strays derive from D/S diodes and
Cu Cu
wiring capacitance
Cu
• VTF is modified due to strays
Cu Cu • Strays at the summing node is of no
significance (virtual ground)
C1 C2
–9–
Professor Y. Chiu
EECT 7327
Stray-Insensitive SC Integrator
Spring 2011
C2
Ф2(Ф1) A C1 B Ф2
Vi
Vo
Ф1(Ф2) Ф1
“Inverting” “Non-inverting”
VTF: C 1 VTF: C1 z 1
H  z   1 H  z  
C2 1  z 1 C2 1  z 1
• Capacitors can be significantly sized down to save power/area

• Sizes are eventually limited by kT/C noise, mismatch, etc.
– 10 –
Professor Y. Chiu
EECT 7327
SC Amplifier
Spring 2011
Ф1
C2
Ф1 C1 C1 1
VTF: H  z   z
Vi C2
Vo
Ф2
• Non-integrating, memoryless (less the delay)

• Used in many applications of parametric amplification
– 11 –
Professor Y. Chiu
EECT 7327
Spring 2011
SC Applications
– 12 –
Professor Y. Chiu
EECT 7327
CT Filter
Spring 2011
R L
Vi C Vo RLC prototype

R2
R4
CA R CB
Active-RC
R1 R R3 Tow-Thomas
Vi
Vo CT biquad
– 13 –
Professor Y. Chiu
EECT 7327
SC DT Filter
Spring 2011
R2
R4
CA R CB
Active-RC
R1 R R3 Tow-Thomas
Vi
Vo CT biquad

C2 Ф1
CA C4 CB Ф2
Ф2 C1 Ф2 Ф1 C3 Ф2
Ф2 SC DT
Vi biquad
Vo
Ф1 Ф1 Ф2 Ф1
– 14 –
Professor Y. Chiu
EECT 7327
Sigma-Delta (ΣΔ) Modulator

Spring 2011
CI
Ф1 CS Ф2
Vi
Do
Ф2 Ф1
+VR 1-b
-VR DAC
DTI + 1-bit comparator + 1-bit DAC = first-order ΣΔ ADC
– 15 –
Professor Y. Chiu
EECT 7327
Pipelined ADC
Spring 2011
Φ2
Φ1 C1
Vi
Φ1 C2
-VR/4 Vo
VR/4 Φ1
-VR Φ2
1.5-b
0
DAC
VR
SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC
– 16 –
Professor Y. Chiu
EECT 7327
SC Common-Mode Feedback
Spring 2011
Vo+ R Vo+ R
A
Vo- R
 A
Vo- R
Vcmc Vcmc
VBias Vcm Vcm-VBias
CM sense amp can be replaced by a floating voltage source since the gain
through the main op-amp is high enough.
– 17 –
Professor Y. Chiu
EECT 7327
SC Common-Mode Feedback
Spring 2011
Ф2 Ф1
Vcm
+
Vo
C Ф2 0.2C Ф1
A VBias
V o- C Ф2 0.2C Ф1
Vcm
Vcmc
Vo+ Vcm-VBias
Ф1
 A
Vo- Vcm-VBias
Ф2 Vcmc
– 18 –
Professor Y. Chiu
EECT 7327
Spring 2011
Noise in SC Circuits
– 19 –
Professor Y. Chiu
EECT 7327
Noise of CT Integrator
Spring 2011
H1(f)
C C
R VN12 R
Vi
Vo Vo
VN22
H2(f)
VN 12 VN 2 2
 f   H1  f   f   H2  f 
2 2
VoN 2
 df   df  
f f
Noise in CT circuits can be simulated with SPICE (.noise)
– 20 –
Professor Y. Chiu
EECT 7327
Noise of SC Integrator
Spring 2011
C2
Ф1 C1 Ф2
Vi
Vo
Ф2 Ф1
Ф1 Ф2 Ф1 Ф2 Ф1 Ф2
SC circuits are NOT noise-free! Switches and op-amps introduce noise.
– 21 –
Professor Y. Chiu
EECT 7327
Sampling (Ф1) Ideal Voltage Source

Spring 2011
VN12 R1 C1 VN22
Vi
R2
 VN 12 VN 2 2 
VN  1    f  f    H1  f 
2 2
 df
0
  f  f 
2
 1
   4kTR1  4kTR2   df
0 1  j 2 f   R1  R2  C
kT

C
• Noise is indistinguishable from signal after sampling
• The noise acquired by C1 will be amplified in Ф2 just like signal
– 22 –
Professor Y. Chiu
EECT 7327
Integration (Ф2)
Spring 2011
H34(f)
C2
VN32 C1 VN42 R4
Vo
R3
VN52
H5(f)
VN 32 VN 4 2  VN 52
VN   2      f  f    H 34  f   f   H5  f 
2 2
2
df   df  
 f f  f
2
C 
  1  VN  1  VN   2 
2 2 2
VoN
 C2 
No simulator can directly simulate the aggregated output noise!
– 23 –
Professor Y. Chiu
EECT 7327
Sampling (Ф1) Noise – Cascaded Stages

Spring 2011
C2 C2'
Ф2 C1 Ф1 Ф1 C1' Ф2
Ф2
Vi
Vo
Ф1 Ф2 Ф2 Ф1

C2
VN32 C1 VN42 R4 VN12 R1 C1' VN22
R3
VN52 R2
• Finite op-amp BW limits the noise bandwidth, resulting in less overall kT/C noise
(noise filtering).
• But parasitic loop delay may introduce peaking in freq. response, resulting in more
integrated noise (noise peaking).
– 24 –
Professor Y. Chiu
EECT 7327
Sampled Noise Spectrum

Spring 2011
CT PSD
0
fs 2fs
Alias
DT PSD
0
fs/2 fs 3/2fs
• Total integrated noise power remains constant

• SNR remains constant
– 25 –
Professor Y. Chiu
EECT 7327
Spring 2011
Nonideal Effects in
SC Circuits
– 26 –
Professor Y. Chiu
EECT 7327
Nonideal Effects in SC Circuits

Spring 2011
• Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich, gate cap,

accumulation-mode gate cap, etc.)
– PP, MIM, and MOM are linear up to 14-16 bits (nonlinear voltage
coefficients negligible for most applications)
– Gate caps are typically good for up to 8-10 bits
• Switches (MOS transistors)
– Nonzero on-resistance (voltage dependent)
– (Nonlinear) stray capacitance added (Cgs, Cgd, Cgb, Cdb, Csb)
– Switch-induced sampling errors (charge injection, clock feedthrough,
junction leakage, drain-source leakage, and gate leakage)
• Operational amplifiers
– Offset
– Finite-gain effects (voltage dependent)
– Finite bandwidth and slew rate (measured by settling speed)
– 27 –
Professor Y. Chiu
EECT 7327
Spring 2011
Nonideal Effects of
Switches
– 28 –
Professor Y. Chiu
EECT 7327
Nonzero On-Resistance
Spring 2011
C
Ron
Ф PMOS
VGS
… NMOS
VTp VTn
Vout CS
CMOS
Ф
0 Vout VDD
…
CS W
1
Ron  Cox VDD  Vth  Vout 
Ф L
• FET channel resistance (thus tracking bandwidth) depends on signal level

• Usually (RonCS)-1 ≥ (3-5)·ω-3dB of closed-loop op-amp for settling purpose
– 29 –
Professor Y. Chiu
EECT 7327
Clock Bootstrapping
Spring 2011
Ф
Ф1 Ф2
…
CS VDD
In Out
Ф M1
CMOS Bootstrapped NMOS
• Small on-resistance leads to large switches → large parasitic caps and

large clock buffers
• Clock bootstrapping keeps VGS of the switch constant → constant on-
resistance (body effect?) and less parasitics w/o the PMOS
– 30 –
Professor Y. Chiu
EECT 7327
Simplified Clock Bootstrapper

Spring 2011
Ф1 Ф2
VDD
In Out
Pros
M1
VDD • Linearity
• Bandwidth
Ф2 M2 Ф2 Cons
• Device reliability
Ф2
C • Complexity
Ф1 Ф1
Out
M1
Ф2
In
VSS
– 31 –
Professor Y. Chiu
EECT 7327
Switch-Induced Errors
Spring 2011
Zi Cgs Cgd • Clock feedthrough

Vout
• Charge injection
Vin Qch CS
Channel charge injection and clock feedthrough (on drain side) result in
charge trapped on CS after switch is turned off.
– 32 –
Professor Y. Chiu
EECT 7327
Clock Feedthrough and Charge Injection

Spring 2011
VDD Vin+Vth
Zi Cgs Cgd
Vout Ф
0
Vin Qch CS
Switch on Switch off
• Both phenomena sensitive to Zi, CS, and clock rise/fall time

• Offset, gain error, and nonlinearity introduced to the sampling
• Clock feedthrough can be simulated by SPICE, but charge injection
cannot be simulated with lumped transistor models
– 33 –
Professor Y. Chiu
EECT 7327
Clock Rise/Fall-Time Dependence

Spring 2011
VDD Vin+Vth
Zi Cgs Cgd
Vout Ф
0
Vin Qch CS
Switch on Switch off
Clock feedthrough Charge injection
C gs CoxWL VDD  Vth  Vin 

V   VDD V  
Fast turn-off
C gs  CS 2 C gs  CS 
C gs
Slow turn-off V   Vin  Vth  V  0
C gs  CS
– 34 –
Professor Y. Chiu
EECT 7327
Dummy Switch
Spring 2011
Ф Ф
Vin Vout
W W
L 2L CS
• Difficult to achieve precise cancellation due to the nonlinear

dependence of ΔV on Zi, CS, and clock rise/fall time
• Sensitive to the phase alignment between Ф and Ф_
– 35 –
Professor Y. Chiu
EECT 7327
CMOS Switch
Spring 2011
Same size for

Vin Vout
P and N FETs
CS
Ф
• Very sensitive to phase alignment between Ф and Ф_

• Subject to threshold mismatch between PMOS and NMOS
• Exact cancellation occurs only for one specific Vin (which one?)
– 36 –
Professor Y. Chiu
EECT 7327
Differential Signaling
Spring 2011
Vip Vop
M1
CSp
Ф Balanced diff. input
Vin Von
M2
CSn
• Signal-independent errors (offset) and even-order distortions cancelled

• Gain error and odd-order nonlinearities remain
– 37 –
Professor Y. Chiu
EECT 7327
Switch Performance
Spring 2011
1 L2 L2
On-resistance: R on   
μC ox
W
 VDD  Vth  Vi  μC ox WL  VDD  Vth  Vi  μQ ch
L
1 μQ
Bandwidth: BW   2 ch
Ron CS L CS
1 Qch
Charge injection: ΔV 
2 CS
ΔV 1 Q ch L2 C S L2
Performance FoM: ≈  =
BW 2 C S μQ ch 2μ
Technology scaling improves switch performance!
– 38 –
Professor Y. Chiu
EECT 7327
Leakage in SC Circuits
Spring 2011
Φ1 = “high”, Φ2 = “low”
C2 Vo(t)
Ф2 Ф2
C1
Vx
Vi
Vo
I3
Ф1 Ф1 I2 I1 A0 Ф1 Ф2 Ф1 Ф2
VB 0 t
• I1 – diode leakage (existing in the old days too)

• I2 – sub-threshold drain-source leakage of summing-node switch
• I3 – gate leakage (FN tunneling) of amplifier input transistors
• Leakage currents are highly temperature- and process-dependent; the
lower limit of clock frequency is often determined by leakage
– 39 –
Professor Y. Chiu
EECT 7327
DS Leakage
Spring 2011
Ф2
VDD CS+
• 0.13-μm CMOS
Ф1 CS+ Ф1e
M1+
• A0 = Gm·Ro = 90dB
Vi+ Vo+ Ф2e
• Ro ≈ 2MΩ
Vi - Vo- Ф2e • Rleak ≈ 0.6V/3μA
M1-
Ф1 CS -
Ф1e
Ф2
VDD C S- ≈ 0.2MΩ
• A0 = Gm·(Rleak//Ro)
VDD = 1.2V ≈ 70dB
Φ
M2 Ileak
M3 M4 Φ Φ
Φ
Φ VDD
Φ
In Out
Φ Φ M1
Out
M1
Φ
Φ In
VSS = 0V
– 40 –
Professor Y. Chiu
EECT 7327
Gate Leakage
Spring 2011
I GS  WL  exp  tox   expVGS 
• Direct tunneling through the thin gate oxide

• Short-channel MOSFET behaves increasingly like BJT’s
• Violates the high-impedance assumption of the summing node
– 41 –
Professor Y. Chiu
EECT 7327
Switch Size Optimization

Spring 2011
• To minimize switch-induced error voltages, small transistor size,

slow turn-off, low source impedance should be used.
• For fast settling (high-speed design), large W/L should be used, and
errors will be inevitably large as well.
Guidelines
• Always use minimum channel length for switches as long as
leakage allows.
• For a given speed, switch sizes can be optimized w/ simulation.
• Be aware of the limitations of simulators (SPICE etc.) using lumped
device models.
– 42 –
Professor Y. Chiu
EECT 7327
Spring 2011
Nonideal Effects of
Op-Amps
– 43 –
Professor Y. Chiu
EECT 7327
Nonideal Effects of Op-Amps

Spring 2011
• Offset
• Finite-gain effects (voltage dependent)
• Finite bandwidth and slew rate (measured by settling
speed)
– 44 –
Professor Y. Chiu
EECT 7327
Offset Voltage
Spring 2011
C2
Vi
Ф1 C1 Ф2
 Q   V  n C  V  n   V C
1 i 1 o os 2
Vo
Ф2 Ф1
 Q   V C1  Vo  n  1  Vos C2
Vos
2 os
C 
Vo(t) Vi  0  Vo  n  1  Vo  n    1 Vos
 C2 
C1 z 1
Vo  z   1 i  
V z
Ф1 Ф2 Ф1 Ф2 C2 1  z
0 t
Vi = 0
– 45 –
Professor Y. Chiu
EECT 7327
Autozeroing
Spring 2011
 Q   V  n  V C
Ф1
1 i os 1  VosC2
C2 Ф2
Ф1 C1 Ф1  Q   V
2 os C1  Vo  n   Vos C2
Vi
Vo
Ф2 Vos
Vo  z  C1
H  z  
Vi  z  C2
• Also eliminates low-frequency noise, e.g., 1/f noise

• A.k.a. correlated double sampling (CDS)
– 46 –
Professor Y. Chiu
EECT 7327
Chopper Stabilization
Spring 2011
Vn2
A B
Vi A1 A2 Vo
fC
1
-1
Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, “A low-noise

chopper-stabilized differential switched-capacitor filtering technique,” IEEE Journal of
Solid-State Circuits, vol. 16, issue 6, pp. 708-715, 1981.
– 47 –
Professor Y. Chiu
EECT 7327
Chopper Stabilization
Spring 2011
|Vi|2
Vn2 0
A B fC f
Vi A1 A2 Vo
SN(f)
fC
1 0
-1 fC f
2
|VA|
0
Also eliminates DC offset fC f
2
|VB|
voltage of A1
0
fC f
– 48 –
Professor Y. Chiu
EECT 7327
Chopper-Stabilized Differential Op-Amp

Spring 2011
Ф Ф
Vi+
Ф Ф
Vo+
Vo-
Ф Ф
Vi-
Ф Ф
• Integrators/amplifiers can be built using these op-amps

• Some oversampling is useful to facilitate the implementation
– 49 –
Professor Y. Chiu
EECT 7327
Ideal SC Amplifier
Spring 2011
Ф1
C2
Ф1 C1 C1
ACL 
Vi C2
X ∞ Vo
Ф2
• Closed-loop gain is determined by the capacitor ratio by design

• But this is assuming X is an ideal summing node (the op-amp is ideal)
– 50 –
Professor Y. Chiu
EECT 7327
Finite-Gain Effect in SC Amplifier

Spring 2011
Ф1
C2
Vo C1 1 C  C  C2 
C1 ACL     1  1  1 
Ф1 Vi C2 1  C1  C2 C2  C2 A 
Vi
X A Vo C2 A
Ф2
 Q     V     V      C
1 i 1 x 1 1  0  C2  Q     V     C
2 x 2 1  Vo  2   Vx  2    C2
Vx  1   Vo  1   Vx  1   A Vo  2   Vx  2   A
Q    Q  
1 2  Vi  C1  Vx  C1   Vo  Vx   C2
Vo  Vx  A
– 51 –
Professor Y. Chiu
EECT 7327
Spring 2011
Practical Issues
– 52 –
Professor Y. Chiu
EECT 7327
Analog vs. Digital Supply Lines

Spring 2011
VA  VDD  VL  VR

did
VL  L VR  id R
dt
id=
Pad
Analog Digital
VDD CBP
circuits circuits
Pad
Sharing sensitive analog supplies with digital ones is a very bad idea.
– 53 –
Professor Y. Chiu
EECT 7327
Analog vs. Digital Supply Lines

Spring 2011
id =
Pad • Dedicated pads
for analog and
digital supplies
Pad
• On-chip bypass
capacitors help
Analog Digital (watch ringing)
VDD CBP
circuits circuits
• Off-chip chokes
(large inductors)
Pad
can stop noise
propagation at
board level
Pad
– 54 –
Professor Y. Chiu
EECT 7327
“Supply” Capacitance
Spring 2011
C2
VDD
Cp
… M5 M7
C stray
Vo  V 
Cgs C2
Ф1 C1 Ф2 S
Vi M1 M2 Vo
X
Ф2 Ф1
Cgd Y CC
M3 M4 M6
VSS
• Any summing-node stray capacitance can be a potential coupling path.

• VDD, VSS, substrate, clock line, and digital noises, body effect, etc.
• Fully differential circuits help to reject common-mode noise and coupling.
– 55 –
Professor Y. Chiu
EECT 7327
“Supply” Capacitance
Spring 2011
C2
Cbot
p+
p well
n substrate
• Avoid connecting bottom-plate parasitics to the summing node

• Avoid crossing other signal lines with the summing node
• Shielding can mitigate substrate noise coupling
– 56 –
Professor Y. Chiu
EECT 7327
Clock Generation
Spring 2011
CLK Ф2
Ф2
Ф1
Ф1
• Clock-gated ring structure

• Non-overlapping time determined by inverter delays, sensitive to process,
voltage, and temperature (PVT) variations
• DLL is an alternative, often used in high-speed designs
– 57 –

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Spring 2011

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Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT 7327 Spring 2011

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Data Converters Switched-Capacitor Circuits

Approach: emulating resistors with switched capacitors

Concept of Switched Capacitor

• A switched capacitor is a discrete-time “resistor”

Shunt-type Series-type 2-phase clock

• Shunt- and series-type SCs are simple and cheap to implement

Discrete-Time Integrator (DTI)

What are the VTFs (z-domain) of these DTIs, assuming no parasitic

Charge conservation law (ideal):

• Capacitors can be significantly sized down to save power/area

• Non-integrating, memoryless (less the delay)

Sigma-Delta (ΣΔ) Modulator

DTI + 1-bit comparator + 1-bit DAC = first-order ΣΔ ADC

SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC

VBias Vcm Vcm-VBias

Noise in CT circuits can be simulated with SPICE (.noise)

SC circuits are NOT noise-free! Switches and op-amps introduce noise.

Sampling (Ф1) Ideal Voltage Source

No simulator can directly simulate the aggregated output noise!

Sampling (Ф1) Noise – Cascaded Stages

VN32 C1 VN42 R4 VN12 R1 C1' VN22

Sampled Noise Spectrum

• Total integrated noise power remains constant

Nonideal Effects in SC Circuits

• Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich, gate cap,

• FET channel resistance (thus tracking bandwidth) depends on signal level

CMOS Bootstrapped NMOS

• Small on-resistance leads to large switches → large parasitic caps and

Simplified Clock Bootstrapper

Zi Cgs Cgd • Clock feedthrough

Clock Feedthrough and Charge Injection

• Both phenomena sensitive to Zi, CS, and clock rise/fall time

Clock Rise/Fall-Time Dependence

Clock feedthrough Charge injection

C gs CoxWL VDD  Vth  Vin 

• Difficult to achieve precise cancellation due to the nonlinear

Same size for

• Very sensitive to phase alignment between Ф and Ф_

• Signal-independent errors (offset) and even-order distortions cancelled

Technology scaling improves switch performance!

• I1 – diode leakage (existing in the old days too)

I GS  WL  exp  tox   expVGS 

• Direct tunneling through the thin gate oxide

Switch Size Optimization

• To minimize switch-induced error voltages, small transistor size,

Nonideal Effects of Op-Amps

• Also eliminates low-frequency noise, e.g., 1/f noise

Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, “A low-noise

Chopper-Stabilized Differential Op-Amp

• Integrators/amplifiers can be built using these op-amps

• Closed-loop gain is determined by the capacitor ratio by design

Finite-Gain Effect in SC Amplifier

Analog vs. Digital Supply Lines

VA  VDD  VL  VR

Analog vs. Digital Supply Lines

• Any summing-node stray capacitance can be a potential coupling path.

• Avoid connecting bottom-plate parasitics to the summing node

• Clock-gated ring structure

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