MOS Integrated Circuits – Basics

BY:-
Ajay Pratap Singh

VLSI Design 1
 Basic Circuits using MOS Transistors
MOS transistors can be used in TWO ways to realize logic functions
1. As Switches (Pass Transistors)
2. As Gates
Pass Transistors
A switch can be closed to pass the current from one terminal to the other
Similarly an MOS transistor can be switched on to pass the signal from
input to output
Vin Vout


When  = 1, Vout = Vin

When MOS transistors are used as switches they are called PASS
transistors
VLSI Design 2
Drawbacks of Pass transistors Vin Vout
Here, when Vin = VDD and =1
Is Vout = VDD ?

(Logic 1 = VDD)
Vin = VDD Vout = ?
No! Now Vout = VDD – V t

Why?
Vin Vout
Say Vin raises from 0.
When Vin = 0, VGS = VDD which is > Vt Hence
the transistor will be ON and Vout = Vin  = 1 = VDD
When Vin = VDD – Vt, VGS = VDD – (VDD – Vt ) =
VDD
Vt and Vout = Vin = VDD – Vt VDD – V t
Vin
0
When Vin > VDD – Vt, VGS < Vt , the transistor
will be OFF and the output can not raise VDD – V t
further and will be clamped to VDD – Vt Vout
0

VLSI Design 3
This leads to another problem
You cannot cascade pass transistors by connecting the output to
the gate of another pass transistor as this will further deteriorate the
output
VDD

VDD
 = VDD
VDD

VDD – Vt

VDD – 2Vt

VDD – 3Vt

You can rectify this problem by using TRANSMISSION GATES

VLSI Design 4
What is a TRSMISSION GATE ?

You can observe that NMOS pass transistors can pass perfect 0
but not perfect 1 from input to output, whereas a PMOS pass
transistor passes perfect 1 but not perfect 0. Here we use
Vt = Vtn = – Vtp
VDD
0 - VDD VDD – Vt VDD – V t VDD – V t
0 Output is clamped
0 to this value
 = VDD
Vin Vout

VDD - 0 Vt
VDD VDD Output is clamped
to this value
=0 Vt Vt
0

Vin Vout

VLSI Design 5
Here we connect NMOS and PMOS transistors in 
parallel and apply  at the gate of NMOS and  at
the gate of PMOS and this is known as
TRANSMISSION GATE.GATE Vin Vout

Let  = 1 and Vin = 0


For NMOS : 0 Vout
VG = VDD and VS = 0  VGS = VDD – 0 = VDD,
VDD
i.e. VGS >> Vt
For PMOS :
0
VG = 0 and VS = 0  VGS = 0 – 0 = 0

0 Vout
This means that PMOS is OFF but NMOS is ON
and hence it will pass the input to the output
So Vout = Vin = 0

VLSI Design 6
PMOS will be OFF until Vin = Vt 

Now, Let  = 1 and Vin = Vt

Vt Vout

For NMOS :
 =1
VG = VDD and VS = Vt  VGS = VDD – Vt,
Vt Vout
i.e. VGS >> Vt
VDD
For PMOS :
VG = 0 and VS = Vt  VGS = 0 – Vt = – Vt 0

This means that the NMOS is fully ON and the Vt Vout

PMOS is just ON and hence they will pass the input
to the output
So Vout = Vin = Vt

VLSI Design 7
The output will continue to follow the input until 
Vin = VDD – Vt

Now, Let  = 1 and Vin = VDD – Vt VDD – Vt Vout

For NMOS :
 =1
VG = VDD and VS = VDD – Vt
 VGS = VDD – (VDD – Vt ) = Vt , i.e. VGS = Vt
VDD – Vt Vout
For PMOS :
VG = 0 and VS = VDD – Vt VDD

 VGS = 0 – (VDD – Vt ) = – VDD + Vt, i.e. VGS << – Vt

0
This means that the PMOS is fully ON and the
NMOS is just ON and hence they will pass the
input to the output VDD – Vt Vout

So Vout = Vin = VDD – Vt

VLSI Design 8
Now, Let  = 1 and Vin > VDD – Vt 
Say Vin = VDD – 0.5 Vt
For NMOS : Vin = VDD –0.5 Vt Vout

VG = VDD and VS = VDD – 0.5Vt


 VGS = VDD – (VDD – 0.5Vt) = 0.5 Vt
Vin = VDD –0.5 Vt Vout
i.e. VGS < Vt
For PMOS : VDD
VG = 0 and VS = VDD – 0.5Vt ,
0
 VGS = – VDD + 0.5Vt , i.e. VGS << – Vt

This means that NMOS is OFF but PMOS Vin = VDD –0.5 Vt Vout
is ON and hence it will pass the input to
the output
So Vout = Vin = VDD – 0.5Vt

VLSI Design 9
Another problem with the pass transistors is that the output is
unpredictable when the gate voltage is 0

Consider the following circuit

VDD X When A = B = C = D = VDD

 ?
X = A.B.C.D
A B C D

Is X = 0 when any one or more of A, B, C. D is 0?

In fact the value of X depends on its previous value which can be either
0 or 1

You have to use additional circuits to get the correct value of the output

VLSI Design 10
The following circuit represents the complete AND gate

VDD
X

A B C D

A B C D

Here X = A . B . C . D

Similarly other logic operations can be obtained using pass transistors

Can you draw a Transmission gate equivalent of the above circuit?

VLSI Design 11
 Gates
MOS transistors can be used in the form of GATEs. The basic circuit of
this type is an INVERTER

Inverters
NMOS Inverter
Consider the circuit consisting of a resistor Rpu
VDD
and an enhancement type NMOS transistor
connected as shown
Rpu
The resistor is known to be the pull-up resistor
Vout and the transistor is known to be the pull-down
G D transistor as they help respectively in pulling-
Vin
S up the output from 0 (0 V) to 1 (VDD) and
pulling-down the output from 1 to 0
This circuit performs the function of inverting
the input to the output

VLSI Design 12
 VDD
The output of the inverter
is usually connected to the
RL
input of another inverter or
a gate, which corresponds
G
D to a capacitive load
Vin
Vout equivalent to the gate-
S
1 1 source capacitance of the
0 0 next stage

How does this circuit work as an inverter?

When Vin = 0, the pull-down transistor is OFF offering a very high
resistance across its output. Hence the output capacitor charges to VDD
( logic 1), through Rpu
When Vin = 1, the pull-down transistor is switched ON offering a low
resistance across its output. Now the capacitor discharges from 1 to 0
through the pull-down transistor

VLSI Design 13
Resistor pull-ups are usually not used because they occupy a very large
area

Instead of Resistor Pull-up you can use other forms of pull-up

mechanisms

Replace Rpu by a Depletion type NMOS with its Gate tied to its Source

VDD How does this work as an inverter?

D Here for the depletion mode transistor, since
G
RL VGS = 0, it is always ON and offers a resistance
S
across its output and thus can be considered
equivalent to a resistor
Vin Vout
However, its resistance is a dynamic one. The
resistance of the pull-up transistor is low when the
output is charging and increases to a high value
when the output discharges

VLSI Design 14
 The supply voltage VDD is shared
VDD
between the pull-up and pull-down
transistors

If the voltage across the pull-up

transistor increases that across the pull-
down transistor decreases and vice-
Vout versa
Vin

The exact value of voltage at any

moment of time can be obtained by
considering the volt-ampere
characteristics of both the pull-up and
pull-down transistors

VLSI Design 15
For the pull-up transistor, it is only a single characteristic corresponding
to VGS = 0 and for the pull-down transistor it is a family of characteristics.
The characteristic of pull-up transistor is superimposed over the
characteristics of pull-down transistor

The points of
intersection of
these
I characteristics give
the values of
currents and
voltages at various
points
0 VDD
(Pull-down) (Pull-down)
(Pull-down)
VDD 0
(Pull-up)
(Pull-up) (Pull-up)

VLSI Design 16
 VDD

I
Vout

Vin

0 , VDD VDD , 0
(Pull-down) (Pull-up)

Initially, when Vin rises from 0 to Vt, (Vt is the threshold voltage of
enhancement transistor) the pull-down transistor just enters into
conduction offering a large resistance at its output and hence a large
output voltage. At this point, the voltage across the pull-up transistor is
VDD – Vout which will be small
Now the pull-down transistor is in SATURATION region and the pull-up
transistor is in RESISTIVE region

VLSI Design 17
 VDD

I
Vout

Vin

0 , VDD VDD , 0
(Pull-down) (Pull-up)
Venh = Vout

Vdep = VDD – Vout

As Vin rises further, the enhancement transistor goes more and more into
conduction making Vout to decrease.
This makes the voltage across the depletion transistor to increase and the
transistor enters from resistive to saturation region

VLSI Design 18
 VDD

I
Vout

Vin

0 , VDD VDD , 0
(Pull-down) (Pull-up)

When Vin  VDD / 2 , the voltage across both the transistors are almost
equal and both are in saturation region.

For further increase in Vin , the pull-down transistor enters into the
resistive region and the output falls to a very low value

VLSI Design 19
 VDD

I
Vout

Vin

0 , VDD VDD , 0
(Pull-down) (Pull-up)

Non-Zero output
The drawbacks are:
1. Non-zero output for logic 0
2. For the entire period for which Vin  Vt, there exists a direct path
between VDD and ground which makes a wasted static current to
flow. This is a wasted power drain to the supply
VLSI Design 20
Transfer Characteristics
VDD

VDD Vout

VDD / 2

Vout

Vin

0 Vt VDD / 2 VDD
Vin

When Vin = 0, Vout = VDD

When Vin = Vt, the pull-down transistor just starts conducting and for
further increase in Vin , the output starts decreasing
When Vin = VDD, Vout decreases to a very low value, but is not perfect zero

VLSI Design 21
CMOS Inverter
VDD

G S

D
Vin Vout
D
G
S

In CMOS inverter depletion mode NMOS is replaced with an

enhancement PMOS and a common input is given to the gates of both the
transistors
The output is taken from the common drain terminals of both the
transistors
Vtn is assumed to be the threshold voltage of NMOS and Vtp is assumed to
be the threshold voltage of PMOS. It is further assumed that Vtp = – Vtn

VLSI Design 22
 Working
1. Vin = 0
VDD Vout = ?
S D
Vin = 0 Vin = 0
G G
D S

Vout = ?

For PMOS, VGS = VG – VS = 0 – VDD = – VDD

i.e. PMOS is fully ON offering a very low resistance at its output

For NMOS, VGS = VG – VS = 0 – 0 = 0

i.e. NMOS is fully OFF offering a very high resistance at its output

No current flows through the inverter and the output is directly connected
to VDD and a good logic 1 is obtained at the output

VLSI Design 23
2. Vin = VDD

This case is similar to Case-1 except that the roles of P and N transistors
are interchanged
VDD Vout = ?
S D
Vin = VDD Vin = VDD
G D G
S

Vout = ?

For PMOS, VGS = VDD – VDD = 0 , i.e. PMOS is fully OFF

For NMOS, VGS = VDD – 0 = VDD , i.e. NMOS is fully ON

Again no current flows through the inverter and the output is directly
connected to Ground through the NMOS and a good logic 0 is obtained at
the output

VLSI Design 24
3. Vin = Vtn
VDD Vout = ?
S D
Vin = Vtn Vin = Vtn
G G
D S

Vout = ?

For PMOS, VGS = VG – VS = Vtn – VDD = – Vtp – VDD , which is highly

negative and hence PMOS is conducting very heavily with low output
resistance and low voltage across it
This corresponds to RESISTIVE region for PMOS
For NMOS, VGS = Vtn , and it just enters into conduction offering a high
output resistance and hence a high voltage across it
This corresponds to SATURATION region for NMOS
The output voltage for this case is the voltage across NMOS and is HIGH,
but the current through the inverter is very small as NMOS offers a high
resistance

VLSI Design 25
4. Vin = VDD – Vtn
This case is similar to Case-3 with the roles of P and N transistors
interchanged
VDD Vout = ?
S D
Vin = VDD – Vtn Vin = VDD – Vtn
G G
D S

Vout = ?

For PMOS, VGS = (VDD – Vtn) – VDD = – Vtn = + Vtp, i.e. PMOS is just
coming out of conduction offering a very high output resistance
This corresponds to SATURATION region for PMOS
For NMOS, VGS = VDD – VT >> VT, hence conducting heavily with low
output resistance
This corresponds to RESISTIVE region for NMOS
The output voltage is LOW, and the current through the inverter is very
small as PMOS offers a high resistance

VLSI Design 26
5. Vin = VDD / 2
VDD Vout = ?
S D
Vin = VDD / 2 Vin = VDD / 2
G G
D S

Vout = ?

For PMOS, VGS = – VDD / 2 and for NMOS, VGS = VDD / 2

So, both PMOS and NMOS are heavily conducting offering low output
resistances
Here both PMOS and NMOS are in SATURATION
This is the region where the inverter exhibits GAIN and the output is
unstable switching from one stable state to the other (0 to 1 or 1 to 0)
The current through the inverter is maximum

VLSI Design 27
Transfer Characteristics
Vt VDD-Vt
VDD

P ON P OFF
Both ON
N OFF N ON
Vout

0 VDD
Vin

1 2 3 4 5

Current
between
VDD and
Ground

0 Vin VDD

VLSI Design 28
 Inverter Design
NMOS Inverter

When an Inverter drives another identical inverter

Vout1 Vout2
Vin1 Vin2

The size of the transistors for the inverters can be determined by

analyzing the volt-ampere characteristics of both N and PMOS

For obtaining the inverter output without degrading, it is assumed that the
following condition is satisfied
Vin1 = Vout1 = Vin2 = Vout2 = Vinv = 0.5 VDD

At this point both the transistors are in saturation

VLSI Design 29
The saturation current for an NMOS is given by

W (VGS – Vt)
2
IDS = K
L 2
Where
L and W are the length and width of the transistor
K is a technology dependent parameter given by K = C0
C0 is the gate capacitance per unit area and
 is the mobility of the channel carriers

Using the suffix ‘pu’ for pull-up and ‘pd’ for pull-down transistors

For the Enhancement Mode transistor, VGS = Vinv

Wpd (Vinv–Vt)2 ……… (1)

 IDS = K
Lpd 2

VLSI Design 30
For the Depletion Mode transistor, VGS = 0 and Vt = Vtd

Wpu (–Vtd)2 ……… (2)

 IDS = K
Lpu 2

Since the current is the same for both the transistors, equating (1) & (2)
we get

Wpd (Vinv–Vt)2 Wpu (–Vtd)2

= ……… (3)
Lpd 2 Lpu 2
Let
Lpd Lpu
Zpd = and Zpu =
Wpd Wpu

Now (3) becomes

1 (Vinv–Vt)2 1 (–Vtd)2
= ……… (4)
Zpd 2 Zpu 2

VLSI Design 31
Substituting the following typical values
Vt = 0.2 VDD, Vt = – 0.6 VDD and Vinv = 0.5 VDD

We get

1 (0.5–0.2)2 1 (+0.6)2
=
Zpd 2 Zpu 2

Zpu 0.36
= = 4 ……… (5)
Zpd 0.09

What does (5) mean?

If an inverter drives another inverter directly then, the size of the pull-up
transistor is 4 times the size of the pull-down transistor

VLSI Design 32
You can get the ratio Zpu/ Zpd = 4 by choosing different values for Lpd, Wpd,
Lpu and Wpu

For example, you can choose Lpd = Wpd = X , Wpu = X and Lpu = 4 X

You can also choose Lpd = X, Wpd = 2X , Wpu = X and Lpu = 2 X

VDD VDD

4:1 2:1

1:1 1:2

VLSI Design 33
When an Inverter drives another inverter through one or more pass
transistors
VDD VDD
Inverter 1 Inverter 2
Vout1
Vout2
Vin1 Vin2

You know that the NMOS pass transistors degrade logic 1 at their
outputs. In other words, when Vout1 = VDD corresponding to Vin1 = 0, Vin2
= VDD – Vt(pass) . For this the output voltage Vout2 will not be a proper logic
0
You already know that for an NMOS inverter, even when the input is VDD
the output is not a perfect zero and to add to it, the deterioration of the
input to the second inverter by the pass transistors deteriorates the
output further

VLSI Design 34
So, you should aim to achieve an output Vout2 for the inverter 2, driven
with an input Vin2 = VDD – Vt(pass) , same as would be the output Vout1 for the
inverter 1 driven with an input Vin1 = VDD
Thus, for inverter 1, Vin1 = VDD and Vout1 = logic 0

i.e., the voltage across the pull-down transistor is low and that across
pull-up transistor is high
This corresponds to the pull-up transistor working in saturation region
and the pull-down transistor in resistive region

For inverter 2, Vin2 = VDD – Vt(pass) and Vout2 = logic 0

Here also, the voltage across the pull-down transistor is low and that
across pull-up transistor is high
This corresponds to the pull-up transistor working in saturation region
and the pull-down transistor in resistive region

VLSI Design 35
Inverter 1
For the Enhancement Mode pull-down transistor (working in RESISTIVE
region)

Wpd1 VDS12
IDS1 = K (VDD–Vt) VDS1 – ……… (6)
Lpd1 2

Since VDS1 is small, neglecting the higher order term, the resistance
offered at the output of the pull-down transistor can be given by

VDS1 1 Lpd1 1
R1  =
IDS1 K Wpd1 (VDD–Vt)

1 1 ……… (7)
= Zpd1
K (VDD–Vt)

VLSI Design 36
For the Depletion Mode pull-up transistor (working in SATURATION
region)

Wpu1 (– Vtd) 2
IDS1 = K ……… (8)
Lpu1 2

Wpu1 (– Vtd) 2 1 1
 Vout1 = IDS1 R1 = K X Zpd1
Lpu1 2 K (VDD–Vt)

Zpd1 1 (– Vtd) 2
= ……… (9)
Zpu1 (VDD–Vt) 2

VLSI Design 37
Inverter 2
Similarly for the inverter 2 the resistance offered at the output of the pull-
down transistor is given by

1 1 ……… (10)
R2  Zpd2
K (VDD–Vt(pass)) – Vt

and the current through the pull-up transistor is given by

1 (– Vtd) 2
IDS2 = K ……… (11)
Zpu2 2

and the output voltage is given by

Zpd2 1 (– Vtd) 2
 Vout2 = IDS2 R2 = ……… (12)
Zpu2 (VDD–Vt(pass)) – Vt 2

VLSI Design 38
Since output of inverter 2 should be same as the output of inverter 1
under our assumed conditions, we get
Vout1 = Vout2
i.e.

Zpd1 1 (– Vtd) 2 Zpd2 1 (– Vtd) 2

=
Zpu1 (VDD–Vt) 2 Zpu2 (VDD–Vt(pass)) – Vt 2

Zpu2 Zpu1 (VDD–Vt)

= ……… (13)
Zpd2 Zpd1 (VDD–Vt(pass) – Vt)

Substituting the typical values Vt = 0.2 VDD and Vt(pass) = 0.3 VDD in (13)

Zpu2 Zpu1 (1 – 0.2)VDD Zpu1 0.8

= =
Zpd2 Zpd1 (1 – 0.3 – 0.2) VDD Zpd1 0.5
Zpu1
 2 =8
Zpd1

VLSI Design 39
This means that if an inverter is driven by another through one or more
pass transistors, the size of the DRIVEN INVERTER (not the driver)
must be such that Zpu / Zpd  8

CMOS Inverter

For CMOS inverter, when Vin = Vout = 0.5 VDD, both P and N transistors
are in saturation. The saturation current is given by
VDD
IDS =  (VGS – Vt) 2

G S
Where  = K W / L = C0  W / L
D
Hence the current through P and NMOS will Vin Vout
be given by D
G
IDSp = p [(Vin – VDD) – Vtp] S
2
……… (14)

IDSn = n [(Vin – 0) – Vt]2 ……… (15)

VLSI Design 40
Since the same current flows through both VDD
the transistors, we have
G S
IDSp = – IDSn
D
i.e. Vin Vout
D
p [(Vin – VDD) – Vtp] 2 = – n [(Vin – 0) – Vt] 2
G
S

Substituting typical values, Vt = – Vtp = 0.2 VDD and

Vin = 0.5 VDD, we get
p = n

i.e. p Wp n Wn
=
Lp Ln

VLSI Design 41
Since the mobility of electrons is approximately 2.5 times the mobility of
holes, we get

Wp Wn
= 2.5
Lp Ln

It is observed that even for a large variations in  values, there is not

much difference in the transfer characteristics and hence the size of both
P and NMOS transistors are usually kept the same

VLSI Design 42