FPGA

) ) Field programmable gate array

April 2008
• Prepared by :
Muhammad Ziyada
Muhammad Al tabakh
 Contents
• Hardware engineers vs software developers
• FPGA Market
• History of FPGA
• Modern developments
• Architecture
• Design and programming
Hardware designers vs software developers
• The hardware engineers roll up their sleeves
and work for months without a break
• software programmers would sit back and
relax, or play ping-pong, until the hardware
was stable.
• the hardware design would quickly become
a hardware redesign for some perceived
deficiency or new feature request
 VHDL solution
• In the early days, circuits as gate-level
schematics.
• saved by )HDLs).
• allowed us to describe the functionality
• Allowed design to be quickly and easily
represented and simulated
 VHDL
• VHSIC hardware description language
• developed at the behest of the US Department of
Defense
• alternative to huge, complex manuals which were
subject to implementation-specific details
• logic simulators were developed to read the
VHDL files
• logic synthesis tools that read the VHDL
 FPGA market
• FPGA Market Will Reach $2.75 Billion by Decade’s
End
 FPGA market
• January 2008
• Celoxica Holdings has agreed the $3m sale of its
electronic system level )ESL) business to US firm
Catalytic.
• With this move, we can synthesize the top two
languages for high-level algorithm development
— C and MATLAB — and deliver both software
and hardware implementations
 FPGA market
• Aerospace & Defense
• Automotive
• Broadcast Consumer
• Data Processing and Storage
• Industrial / Scientific / Medical
• Wired Communications
• Wireless Communications
FPGA market
 Brief history
• the invention of the very first
computers in the 1940's and 1950's
• A Xilinx co-founder, Ross Freeman,
invented the field programmable gate array
in 1984
• FPGA come after many earlier devices
 Modern development
• Configurable Logic Blocks
Registers (flip flops) for fast data
storage
. Logic Routing
• Input/Output Blocks
Basic pin logic (flip flops, muxs, etc)
• Block Ram
Internal memory for data storage
• Digital Clock Managers
Clock distribution
• Programmable Routing Matrix
 "Pros" and "Cons"
• Pros
Low power consumption; ideal for portable
electronics devices.
Upgradeable using software, instead of extensive
hardware replacement .
Low cost of overhead .
Sometimes replaces as many as twenty traditional
PALs.
Parallel computing possibilities .
 "Pros" and "Cons"

• Cons
High cost of fabricating a completely new chip
Size constraints / limitations
More difficult to code & debug
Many applications still are, and may remain, in the
theoretical phase
 FPGA vs classical architecture
• Classical operation
Fetch an instruction
Fetch a piece of data
Fetch another piece of data
Perform an operation
Store the result
:
Do the same thing all over again
 FPGA vs classical architecture
• y = )a * b) + )c * d) + )e * f) + )g * h);

• the multiplications are performed in parallel

without the need to fetch and decode the
instructions. This results in orders-of-
magnitude speed improvement.
 FPGA vs conventional circuit
FPGA Costs
$350
Cost per1 Million Gates

$300
$250
$200
$150
$100
$50
$0
1998 1999 2000 2001 2002 2003

80’s 90’s Now

 The rise of FPGA
• The first devices were primitive diode
matrices used in TV channel selectors,
HAM radio tuners, emerging defense and
space applications.
• replaced by more capable logic devices
based on arrays of combinatorial gates
• dramatic change in reprogram ability, more
flexible interconnect architectures.
 The rise of FPGA
• Programmable Logic Arrays )PLA)
 The rise of FPGA
• Programmable Array Logic )PAL)
 The rise of FPGA
• Complex PLDs )CPLDs)
 The rise of FPGA
• Field Programmable Gate Arrays )FPGAs)
 Main vendors
• Xilinx spartan and vertix series
ise webback software
• Altera cyclon series
Quartus software
• Mentor Graphic
FPGAdv software
FPGA design

skip
FPGA design
 FPGA programming
Languages
HDL languages ) VHDL and VERILOG )
Truth table
Block diagram
Schematic diagram
Flowchart
State machine
And more
 VHDL code
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1 IS
PORT ) w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux2to1 ;
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
PROCESS ) w0, w1, s )
BEGIN
IF s = '0' THEN
f <= w0 ;
ELSE f <= w1 ;
END IF ;
END PROCESS ;
END Behavior ;;
 Soft cores
• MicroBlaze,PowerPC,Nios,… soft
processor
• create complete systems composed of, for
example, an 8- or 16-bit controller, a
UART, and other such I/O devices on a
single programmable chip
Soft processor
 References
• Practical FPGA Programming in C
By David Pellerin, Scott Thibault

• Ece230 vhdl lectures

By Khurram Waheed

• VHDL cookbook
By peter j.ashenden
 Thank you

Muhammad ziyada
modeonz007@yahoo.com
20113246609+
Muhammad al tabakh
nooo_impossible@yahoo.com
20121539035+