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T H E A R C H I T E C T U R E F O R T
TM H E D I G I T A L W O R1 L D
Day 9 Agenda
Introduction
The ARM Architecture Overview
Programmers Model
Instruction Set
ARM { x } { y } { z } { T } { D } { M } { I } { E } { J } { F } { -S }
x – Family
Y – Memory Management/Protection Unit
Z – Cache
T – THUMB 16 - Bit Decoder
D – JTAG Debug
M – Fast Multiplier
I – Embedded ICE Macrocell
E – Enhanced Instruction (Assumes TDMI)
J – Jazelle
F – Vector Floating Point Unit
S – Synthesizable Version
Architecture
Versions 1 and 2 -- Acorn RISC, 26-bit address
Version 3 – 32-bit address, CPSR, and SPSR
Version 4 – half-word, Thumb
Version 5
Processor cores
ARM7TDMI (Thumb, debug, multiplier, ICE) –
version 4T, low end
ARM core, 3-stage pipeline
ARM9TDMI – 5-stage pipeline
ARM10TDMI – version 5
CPU Core: co-processor, MMU, AMBA
ARM 710, 720, 740
ARM 920, 940
PC
Instruction Add Sum
Instruction MemWrite
memory
Address Read
data 16 32
a. Instruction memory b. Program counter c. Adder Sign
extend
Write Data
ALU control data memory
5 Read 3
register 1
Read
Register 5 data 1
Read MemRead
numbers register 2 Zero
Registers Data ALU ALU
5 Write result a. Data memory unit b. Sign-extension unit
register
Read
Write data 2
Data data
RegWrite
a. Registers b. ALU
M
Add u
x
4 Add ALU
result
Shift
left 2
Registers
Read 3 ALU operation
MemWrite
Read register 1 ALUSrc
PC Read
address Read data 1 MemtoReg
register 2 Zero
Instruction ALU ALU
Write Read Address Read
register M result data
data 2 u M
Instruction u
memory Write x Data x
data memory
Write
RegWrite data
16 32
Sign
extend MemRead
op rs rt rd shamt funct
op rs rt rd shamt funct
35 2 1 100
op rs rt 16 bit offset
000 AND
001 OR
010 add
110 subtract
111 set-on-less-than
Instruction [5– 0]
Introduction
The ARM Architecture Overview
Programmers Model
Instruction Set
cpsr
spsr spsr spsr spsr spsr spsr
cpsr
spsr spsr spsr spsr spsr
N Z C V Q J U n d e f i n e d I F T mode
f s x c
Condition code flags Interrupt Disable bits.
N = Negative result from ALU I = 1: Disables the IRQ.
Z = Zero result from ALU F = 1: Disables the FIQ.
C = ALU operation Carried out
V = ALU operation oVerflowed T Bit
Architecture xT only
T = 0: Processor in ARM state
Sticky Overflow flag - Q flag T = 1: Processor in Thumb state
Architecture 5TE/J only
Indicates if saturation has occurred
Mode bits
Specify the processor mode
J bit
Architecture 5TEJ only
J = 1: Processor in Jazelle state
Introduction
The ARM Architecture Overview
Programmers Model
Instruction Set
Consist of :
Arithmetic: ADD ADC SUB SBC RSB RSC
Logical: AND ORR EOR BIC
Comparisons: CMP CMN TST TEQ
Data movement: MOV MVN
These instructions only work on registers, NOT memory.
Syntax:
<Operation>{<cond>}{S} Rd, Rn, Operand2
Comparisons set flags only - they do not specify Rd
Data movement does not specify Rn
Second operand is sent to the ALU via barrel shifter.
Cycle time
Basic MUL instruction
2-5 cycles on ARM7TDMI
1-3 cycles on StrongARM/XScale
2 cycles on ARM9E/ARM102xE
+1 cycle for ARM9TDMI (over ARM7TDMI)
+1 cycle for accumulate (not on 9E though result delay is one cycle longer)
+1 cycle for “long”
Above are “general rules” - refer to the TRM for the core you are using for
the exact details
31 28 27 25 24 23 0
Cond 1 0 1 L Offset
The processor core shifts the offset field left by 2 positions, sign-extends
it and adds it to the PC
± 32 M byte range
How to perform longer branches?
CF Destination 0 Destination CF
Destination CF
Immediate value
8 bit number, with a range of 0-255.
Rotated right through even number of
positions
ALU Allows increased range of 32-bit
constants to be loaded directly into
registers
Result
11 8 7 0
rot immed_8
Quick Quiz:
x2 0xe3a004ff
Shifter
ROR MOV r0, #???
4 bit rotate value (0-15) is multiplied by two to give range 0-30 in steps of 2
Rule to remember is “8-bits shifted by an even number of bit positions”.
or
Generate a LDR instruction with a PC-relative address to read the constant
from a literal pool (Constant data area embedded in the code).
For example
LDR r0,=0xFF => MOV r0,#0xFF
LDR r0,=0x55555555 => LDR r0,[PC,#Imm12]
…
…
DCD 0x55555555
This is the recommended way of loading constants into a register
Syntax:
LDR{<cond>}{<size>} Rd, <address>
STR{<cond>}{<size>} Rd, <address>
e.g. LDREQB
<LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^}
where: {cond} Two character condition mnemonic
Rn An expression evaluating to a valid register number
<Rlist> A list of registers and register ranges enclosed in {} (e.g. {R0,R2-R7,R10}).
{!} If present requests write-back (W=1), otherwise W=0.
{^} If present set S bit to load the CPSR along with the PC, or force transfer of user
bank when in privileged mode.
Condition Field
N Z C V Q J U n d e f i n e d I F T mode
f s x c
where
<psr> = CPSR or SPSR
[_fields] = any combination of ‘fsxc’
Also an immediate form
MSR{<cond>} <psr_fields>,#Immediate
In User Mode, all bits can be read but only the condition flags (_f) can be
written.
func1 func2
STMFD :
: sp!,{regs,lr}
:
: :
:
BL func1 BL func2
:
: :
:
: LDMFD
sp!,{regs,pc} MOV pc, lr
Exceptions
System Design
Memory Interface
Synchronization
Input / Output