ARM assembly language programming

General Layout of an Assembly Program

label opcode operands Example start MOV r0,#15 ; comment

; put 15 into reg. r0

Each field must be separated by one or more <whitespace> (such as a space or a tab). Actual instructions never start in the first column, since they must be preceded by whitespace, even if there is no label. All three sections are optional

Asm program
AREA ARMex, CODE, READONLY ENTRY start : MOV r0, #10 MOV r1, #0x20 ADD r0, r0, r1 stop: B stop END
/* Mark end of file */ /* r0 = r0 + r1 */
/*

Name this block of code ARMex*/

/*

Mark first instruction to execute */

/* Set up parameters */

AREA, ENTRY & END Assembly Directives

Directives are instructions to the assembler program, NOT to the microprocessors AREA Directive - specifies chunks of data or code that are manipulated by the linker.

The example above consists of a single area which contains code and is marked as being read-only. A single CODE area is the minimum required to produce an application. A complete application can consist of one or more areas.

ENTRY Directive - marks the first instruction to be executed within an application

An application can contain only a single entry point and so in a multisource-module application, only a single module will contain an ENTRY directive. Instructs the assembler to stop processing this source file

END directive - marks the end of the module

Assembly Directives

Labels Labels are symbols that represent addresses. The address given by a label is calculated during assembly. The assembler calculates the address of a label relative to the origin of the section where the label is defined. A reference to a label within the same section can use the PC plus or minus an offset. This is called program-relative addressing.

Calling subroutines

Adds the values of two parameters and returns a result in r0. AREA subrout, CODE, READONLY ENTRY

start:

MOV r0, #10 MOV r1, #20 BL doadd

stop:B stop doadd: ADD r0, r0, r1 MOV PC, LR END

subroutine doadd is called by using a branch with link instruction (BL branch address).

BL copies the address of the next instruction into r14 (lr=link register), then fills PC=branch address (go to branch address).

It then returns by simply restoring the program counter to the address which was stored in the link register (r14) on entry.

Description of ex1

The main routine of the program (labelled start ) loads the values 10 and 20 into registers 0 and 1. It calls the subroutine doadd by using a branch with link instruction (BL branch address). BL copies the address of the next instruction into r14 (lr=link register), then fills PC=branch address (go to branch address). The subroutine adds together the two parameters it has received and places the result back into r0. It then returns by simply restoring the program counter to the address which was stored in the link register (r14) on entry.

The S suffix

Data processing instructions of ARM will not modify the condition flags in CPSR. But we can modify the condition flags by appending S bit to the instruction. Example

MOV r3, #00 .. This instruction will not update zero flag. MOVS r3, #00 This instruction will update the zero flag.

Program Status Register

N Z C V I F T 5
M4 4 M3 3 M2 2 M1 1 M0 0

31 30 29 28

7 6

Condition code flags

N = Negative result from ALU is set to bit 31 of result Z = Zero result from ALU C = ALU operation Carried out V = ALU operation Overflowed

Interrupt disable bits (I & F)

I bit When set to 1 disables IRQ interrupts F bit When set to 1 disables FIQ interrupts

T Bit (Architecture xT only)

T = 0: Processor in ARM state T = 1: Processor in Thumb state

M0, M1,M2, M3, M4 are mode bits. These determine the mode in which processor operates. (Tells operating mode of processor)

The S suffix
#AREA ARMex, CODE, READONLY #ENTRY start: MOV r0, #-3 MOV r1, #3 ADD r0, r0, r1 B stop

stop: #END

Result of addition is zero but

Zero flag will not be set

The S suffix
#AREA ARMex, CODE, READONLY #ENTRY start: MOV r0, #-3 MOV r1, #3 ADDS r0, r0, r1 B stop

stop: #END

This example conditional flags of CPSR will be modified because the S suffix is added to ADD instruction

Loop

Write a program that adds value 3 to the register ten times

mov r0,#10 mov r1,#0

C statements for (i=10; i>0;i--) ------

again:

add r1,r1,#3 sub r0, r0,#1

Branch if Z-flag is not set to again mov r0,#10 mov r1,#0 again: add r1,r1,#3 subs r0, r0,#1

Branch if Z-flag is not set to again

ARM instructions

Main features of the ARM Instruction Set

All instructions are 32 bits long. Most instructions execute in a single cycle. Every instruction can be conditionally executed. A load/store architecture

Data processing instructions act only on registers Three operand format Combined ALU and shifter for high speed bit manipulation

Specific memory access instructions with powerful auto-indexing addressing modes.

32 bit and 8 bit data types and also 16 bit data types on ARM Architecture v4. Flexible multiple register load and store instructions

3-address instruction format 2 address instruction format Instruction set extension via coprocessors

ARM instructions

Data processing instructions Load and store instructions Semaphore instructions Multiply instructions Exception generating instruction Branch instructions Coprocessor instruction

Data processing Instructions

Data movement Logical Arithmetic Comparisons

MOV MVN AND ORR EOR BIC ADD ADC SUB SBC RSB RSC CMP CMN TST TEQ

These instructions only work on registers, NOT memory. Syntax: 3 operands - 2 for inputs and 1 for result
<Operation>{<cond>}{S} Rd, Rn, Operand2

All operands are 32 bits, come either from registers or are specified as constants (called literals) in the instruction itself

Data Movement

Operations are:

MOV operand2 MVN NOT operand2

Syntax: <Operation>{<cond>}{S} Rd, Operand2

Note that these make no use of operand1 Examples:

MOVS r2, #10

Barrel shifter

One of the operand of ALU always comes from barrel shifter. This unique & powerful feature allows 32 bit binary pattern of the source register to be shifted left or right before it enters ALU.

Barrel shifter
C statement: int i=10, j; j = I << 2;

MOV

R7, R5, LSL #2

If R5=10 the what is value of R7

Barrel shifter operations

LSL LSR ASR ROR logical shift left logical shift right arithmetic right shift rotate right

ADD

R0, R1, R1, LSL#1

(R0=R0+R0<<n)

ADD R0, R0, R0, LSL#N gives multiplication of R0 by 2n + 1

Logical Operations
Syntax: <Operation>{<cond>}{S} Rd, Rn, N
AND ORR EOR BIC bitwise AND of two 32-bit values bitwise OR of two 32-bit values bitwise XOR of two 32-bit values Logical bit clear Rd Rd Rd Rd = = = = Rn Rn Rn Rn &N |N N & N

Examples:

AND r0, r1, r2 BIC r2, r3, #7 EORS r1,r3,r0

Arithmetic Operations

Operations are:

Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2

ADD operand1 + operand2 ADC operand1 + operand2 + carry SUB operand1 - operand2 SBC operand1 - operand2 - !(carry flag) RSB operand2 - operand1 RSC operand2 - operand1 - !(carry flag)

Examples:

ADDC r0, r1, r2 SBC R0, R1, R2 RSB r0, r1, r2

r0 := r1+ r2 r0 := r1 r2 - !(carry) r0 := r2 r1

Comparisons

The only effect of the comparisons is to UPDATE THE CONDITION FLAGS. Operations are:

CMP operand1 - operand2 CMN operand1 + operand2 TST operand1 AND operand2 TEQ operand1 EOR operand2

but but but but

result result result result

not not not not

written written written written

Corresponding operation is carried out conditional flags are updated depending on the result so that subsequent instruction can be conditionally executed
CMP r1 , r2 r1 r2

Examples:

CMN r1, r2 TST r1, r2 TEQ r1,r2

r1 + r2 r1 and r2 r1 xor r2

Comparisons

TEQ is useful

To test whether two values are equal without

When TEQ is executed, N flag is logical exor of the sign bits of two operands hence we can check whether two values have the same sign. TST is used to check if register bits include at least one bit set.

A common use of TST is to test if single bit is set or clear

Conditional execution

Most ISAs only allow branches to be executed conditionally. But ARM ISA has a unique and clever way of dealing with conditional branches. Instead of having special conditional branch instructions, ARM ISA implements a feature of executing ALL instructions conditionally.

For this every instruction contains a conditional field which determines whether the instruction will be executed or ignored. Thus CPU will execute the instruction only if the condition is satisfied.

Conditional execution depends on two components

Conditional field/code Condition flags

(.............located in instruction) (.............located in CPSR)

Conditional execution

To execute an instruction conditionally, simply postfix it with appropriate condition code: For example an add instruction takes the form:

ADD r0,r1,r2

; r0 = r1 + r2

To execute this only if the zero flag is set: ADDEQ r0,r1,r2 ; If zero flag set then .. r0 = r1 + r2

If <cond> is omitted then it is executed always

Almost all ARM instructions can be conditionally executed

Instruction will be executed only if N,Z,C & V satisfy the condition specified in instruction. If flags do not satisfy the condition instruction acts as NOP & execution advances to next instruction.

Condition Codes

The possible condition codes are listed below:

Suffix EQ NE CS/HS CC/LO MI PL VS VC HI LS GE LT GT LE AL Description Equal Not equal Unsigned higher or same Unsigned lower Minus Positive or Zero Overflow No overflow Unsigned higher Unsigned lower or same Greater or equal Less than Greater than Less than or equal Always Flags tested Z=1 Z=0 C=1 C=0 N=1 N=0 V=1 V=0 C=1 & Z=0 C=0 or Z=1 N=V N!=V Z=0 & N=V Z=1 or N=!V

Conditional execution: example

This improves code density and performance by reducing the number of forward branch instructions.

CMP r3,#0 BEQ skip ADD r0,r1,r2 skip

CMP r3,#0 ADDNE r0,r1,r2

Conditional execution reduces number of branches that reduces number of pipeline flushes and thus improves the performance.

Conditional execution

Conditional execution can replace branch instructions Example

With conditional execution CMP r0, #5 ; ADDNE r1, r1, r0 ; SUBNE r1, r1, r2 ;

CMP r0, #5 ; BEQ BYPASS ; if (r0!=5) r1:=r1+r0-r2 ADD r1, r1, r0 SUB r1, r1, r2 BYPASS: ...

Conditional execution

Use a sequence of several conditional instructions

i f (a==0) CMP ADDEQ MOVEQ r0,#0 r1,r1,#1 r3, #1 {

count =count+1; flag = 1;

Set the flags, then use various condition codes

if (a==0) x=0; if (a>0) x=1;

CMP MOVEQ MOVGT

r0,#0 r1,#0 r1,#1

Conditional execution examples

MOVEQ r0,r1 MOVS r0, r1, LSR #1 MOVCC r0, #10 MOVCS r0, #11

; r0 := r1 if Z flag set ; C(flag) := r1[0] ; if C=0 then r0:=10 ;if C=1 then r0:=11

S flag: determines if the flag fields are affected or not

MOV r1,#10 loop ADD R3, R3,#3 SUBS r1,r1,#1 BNE loop

decrement r1 and set flags if Z flag clear then branch

Conditional execution oring

; if ((a==0) || (b==1)) c = d + e; CMP r0,#0 CMPNE r1, #1 ADDEQ r2, r3, r4

Use conditional compare instruction

if (a==4 || a==10) x=0; CMP r0,#4 CMPNE r0,#10 MOVEQ r1,#0