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8-bit microcontrollers

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CDAC,Mohali

Computer Organization
Control unit

ALU
Memory Register Output Input

Processor
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Overview of PIC16FXX family


Low - end PIC Architectures : Microchip PIC microcontrollers are available in various types. When PIC microcontroller MCU was first available from General Instruments in early 1980's, the microcontroller consisted of a simple processor executing 12-bit wide instructions with basic I/O functions. These devices are known as low-end architectures. They have limited program memory and are meant for applications requiring simple interface functions and small program & data memories. Some of the low-end device numbers are 12C5XX 16C5X 16C505 Mid range PIC Architectures Mid range PIC architectures are built by upgrading low-end architectures with more number of peripherals, more number of registers and more data/program memory. Some of the mid-range devices are 16C6X 16C7X 16F87X

4/17/2012

CDAC,Mohali

The features of the PIC16FXX.


8-bit CPU optimized for control applications Only 35 instructions to learn All single-cycle instructions except branches 8K ROM memory in FLASH technology 368 bytes RAM memory 256 bytes EEPROM memory A/D converter: 14-channels 10-bit resolution
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Contd

35 input/output pins High current source/sink for direct LED drive software and individually programmable pull-up resist Interrupt-on-Change pin In-Circuit Serial Programming Option 3 independent timers/counters Analogue comparator module with Two analogue comparators Programmable on-chip voltage reference Enhanced USART module Supports RS-485, RS-232 and LIN2.0 Auto-Baud Detect Oscillator & Clock Circuit
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Block Diagram of PIC16f877a

4/17/2012

CDAC,Mohali

Other members of the family

4/17/2012

CDAC,Mohali

Pinout diagram of PIC16F877a

4/17/2012

CDAC,Mohali

Pin Description of 16F877a


NAME MCLR/VPP
RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF

NUMBER

FUNCTION 1 MCLR
VPP 2 RA0 AN0 3 RA1 AN1 4 RA2 AN2 VREF CVREF 5 RA3 AN3 VREF+ 6 RA4 T0CKI C1OUT 7 RA5 AN4 SS C2OUT 8 RE0 RD AN5 9 RE1 WR AN6

DESCRIPTION Master Clear (Reset) input. This pin is active low


Programming voltage input. Digital I/O. Analog input 0 Digital I/O. Analog input 1. Digital I/O. Analog input 2. A/D reference voltage (Low) input. Comparator VREF output. Digital I/O. Analog input 3. A/D reference voltage (High) input. Digital I/O Open-drain when configured as output. Timer0 external clock input. Comparator 1 output. Digital I/O. Analog input 4. SPI slave select input. Comparator 2 output. Digital I/O. Read control for Parallel Slave Port. Analog input 5. Digital I/O. Write control for Parallel Slave Port. Analog input 6.

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS/C2OUT

RE0/RD/AN5

RE1/WR/AN6

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CDAC,Mohali

Continued..
RE2/CS/AN7 10 RE2 CS AN7 VDD 11 Digital I/O. Chip select control for Parallel Slave Port. Analog input 7. Positive supply

VSS
OSC1/CLKI

12
13 OSC1 CLKI

Ground
Oscillator crystal input External clock source input. Always associated with pin function OSC1 Oscillator crystal output. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 Digital I/O. Timer1 oscillator output.

OSC2/CLKO

14 OSC2 CLKO

RC0/T1OSO/T1CKI

15 RC0 T1OSO

T1CKI
RC1/T1OSI/CCP2 16 RC1 T1OSI CCP2 RC2/CCP1 RC3/SCK/SCL 17 RC2 CCP1 18 RC3 SCK SCL

Timer1 external clock input


Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. Digital I/O. Capture1 input, Compare1 output, PWM1 output. Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode.

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Continued.
RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA 19 RD0 PSP0 20 RD1 PSP1 21 RD2 PSP2 22 RD3 PSP3 23 RC4 SDI SDA 24 RC5 SDO 25 RC6 TX CK 26 RC7 RX DT 27 RD4 PSP4 Digital I/O. data. Digital I/O. data. Digital I/O. data. Digital I/O. data. Digital I/O. SPI data in. I2C data I/O Digital I/O. SPI data out. Digital I/O. USART asynchronous transmit. USART1 synchronous clock Digital I/O. USART asynchronous receive. USART synchronous data. Digital I/O. data.

RC5/SDO RC6/TX/CK

RC7/RX/DT

RD4/PSP4

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Continued..
RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3/PGM 28 RD5 PSP5 29 RD6 PSP6 30 RD7 PSP7 31 32 33 RB0 INT 34 35 36 RB3 PGM RB4 RB5 RB6/PGC 37 38 39 RB6 PGC 40 RB7 PGD Digital I/O. data. Digital I/O. data. Digital I/O. data. Ground Positive supply Digital I/O. External interrupt. Digital I/O. Digital I/O. Digital I/O. Low-voltage ICSP programming enable pin. Digital I/O. Digital I/O. Digital I/O. In-circuit debugger and ICSP programming clock. Digital I/O. In-circuit debugger and ICSP programming data.

RB7/PGD

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CDAC,Mohali

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Important Terms
Pulse P: It is the smallest interval of time within

microcontroller established by the clock frequency. Machine Cycle: Smallest interval of time to accomplish any simple instruction or part of complex instruction. State: Basic time interval for discrete operations of machine cycles, such as fetching op-code byte, decoding an opcode etc.

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CDAC,Mohali

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Machine cycle in PIC16F877a..


The execution time is the same for all instructions except two and lasts 4 clock cycles (oscillator frequency is stabilized by a quartz crystal). The Jump and Branch instructions execution time is 2 clock cycles. It means that if the microcontrollers operating speed is 20MHz, execution time of each instruction will be 200nS, i.e. the program will be executed at the speed of 5 million instructions per second!
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STATUS REGISTER
IRP
Bit7

RP1

RP0

TO

PD

DC

C
Bit0

bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) Each bank is 128 bytes. bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred
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bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred
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