COMPUTER ENGINEERING

1 CHAPTER 5 INPUT / OUTPUT

Outcomes
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At the end of this topic, students are able to: 1. Define the concept of I/O Interfacing

2. Describe programmed I/O and interrupt driven

I/O, direct memory access

Input/Output Problems
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The reasons why the peripherals are not connected

directly to the system bus: Wide variety of peripherals

Delivering different amounts of data At different speeds In different formats

All slower than CPU and RAM Peripherals often use different data formats and

word lengths Need I/O modules

Input/Output Module
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I/O module has two major functions: Interface to CPU and Memory via the system bus or

central switch Interface to one or more peripherals devices by data links

Generic Model of I/O Module

I/O module is not simply

a set of mechanical connectors, rather, the I/O module contains some intelligence; that is contain logic for performing a communication function between peripheral and bus

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Attaches to the computer by a link to an I/O module The link is used to exchange control, status & data between the

I/O module and the external device Categories of external devices: Human readable

Suitable for communicating with the computer user Screen, printer, keyboard

Machine readable Suitable for communicating with equipment Monitoring and control Communication Suitable for communicating with remote devices Exchange data

External Device Block Diagram

Interface of I/O module is

in the form of control, data and status signals Control determine function that the device will perform Data are in the form of a set of bits to be sent to or received from the I/O module Status indicate the state of the device

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Control logic - associated with the device controls

the devices operation in response to direction from the I/O module Transducer converts data from electrical to other forms of energy during output and from other forms to electrical during input. Buffer associated with transducer to temporarily hold data being transferred between the I/O module and the external environment

I/O Module Function

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Control & Timing to coordinate the flow of

traffic between internal resources and external devices CPU Communication I/O module must communicate with the processor Device Communication - involves commands, status information and data Data Buffering data are buffered in I/O module and sent to peripheral with equivalent data rate Error Detection subsequently reporting errors to processor

I/O Steps
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Ex: control of the transfer of data from an external

device to the processor involve the following steps:

CPU checks I/O module to check device status I/O module returns status If device ready, CPU requests data transfer I/O module gets data from device I/O module transfers data to CPU

I/O Module Diagram

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cont
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Module connects to the rest of the computer through

a set of signal lines. Data transferred to and from the module are buffered in one or more registers. Status register may also function as control register, to accept detailed control information from the processor The logic within the module interacts with the processor via a control lines Processor use the control lines to issue commands to the I/O module

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I/O module must be able to recognize and generate

addresses associated with devices it controls Each I/O module must have unique address I/O module contains logic specific to the interface with each device it controls

Input Output Techniques

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Programmed I/O data are exchanged between the processor and the I/O module. Processor issues a command to the I/O module, it must wait until the I/O operation is complete Interrupt driven Processor issues an I/O command, continues to execute other instructions and interrupted by the I/O module when the latter has completed its work Direct Memory Access (DMA) I/O module and main memory exchange data directly, without processor involvement

Programmed I/O
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CPU has direct control over I/O Sensing status Read/write commands Transferring data CPU waits for I/O module to complete operation Wastes CPU time

Programmed I/O - detail

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When the processor is executing a program and

encounters an instruction relating to I/O:

CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically I/O module does not inform CPU directly I/O module does not interrupt CPU CPU may wait or come back later

I/O Commands
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To execute an I/O instruction: CPU issues address Identifies module CPU issues command Control activate peripheral and telling it what to do

e.g. spin up disk e.g. power? Error? Module obtain data from the peripheral and place in buffer. CPU can obtain data by requesting I/O module to place it on data bus I/O module to take data from data bus and transmit data to the peripheral

Test - check status associated with I/O module and its peripheral

Read

Write

Addressing I/O Devices

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There will be many I/O devices connected through I/O

modules to the system Each device given unique identifier CPU commands contain identifier (address of desired device) I/O module must interpret the address line to determine if the command is for itself When the processor, main memory and I/O share a common bus, 2 modes of addressing are possible:

Memory mapped I/O isolated I/O

I/O Mapping
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Memory mapped I/O Devices and memory share an address space I/O looks just like memory read/write No special commands for I/O Isolated I/O Separate address spaces Need I/O or memory select lines Special commands for I/O

Interrupt Driven I/O

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Overcomes CPU waiting No repeated CPU checking of device I/O module interrupts CPU when ready

CPU executes data transfer, resumes its former

processing

Interrupt Driven I/O Basic Operation

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CPU issues read command I/O module gets data from peripheral whilst CPU

does other work I/O module interrupts CPU over control line CPU requests data I/O module transfers data

CPU Viewpoint
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Issue read command Do other work Check for interrupt at end of each instruction cycle

If interrupted: Save context (registers) Process interrupt

Fetch data & store

Identifying Interrupting Module (1)

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Different line for each module impractical Limits number of devices Software poll Once the CPU detects an interrupt, it branches to an ISR CPU asks each module in turn (poll) Each I/O module contain an addressable status register Processor reads status register to identify the interrupting module Once the module is identified, processor branches to DSR specific to that device Slow

Identifying Interrupting Module (2)

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Daisy Chain or Hardware poll I/O modules share interrupt request line Interrupt Acknowledge sent down a chain Module responsible places vector on bus CPU uses vector to identify handler routine Bus Master Module must claim the bus before it can raise interrupt request line Only one module can raise the line at a time Processor detects interrupts, respond on interrupt acknowledge line Requesting module places its vector on data lines

Direct Memory Access

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Interrupt driven and programmed I/O require active

CPU intervention to transfer data between memory and I/O module

Transfer rate is limited CPU is tied up in managing I/O transfer

DMA is the answer

DMA Function
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Additional Module (hardware) on bus DMA controller takes over from CPU for I/O To transfer data to and from memory over the

system bus DMA module must use the bus only when the processor does not need it Must force CPU suspend operation temporarily cycle stealing

DMA Module Diagram

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DMA Operation
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CPU wish to read/write block of data, it will tells

DMA module by sending information:

Read/Write using w/r control lines Device address involved Starting address of memory block for data Amount of data to be transferred

CPU carries on with other work DMA controller deals with transfer DMA controller sends interrupt when finished

DMA Transfer Cycle Stealing

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DMA controller takes over bus for a cycle Transfer of one word of data Not an interrupt CPU does not switch context CPU suspended just before it accesses bus i.e. before an operand or data fetch or a data write

DMA Configurations (1)

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Share same system bus

Each transfer uses bus twice I/O to DMA then DMA to memory CPU is suspended twice

DMA Configurations (2)

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Single Bus, Integrated DMA controller Controller may support >1 device

Each transfer uses bus once DMA to memory

CPU is suspended once

DMA Configurations (3)

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Separate I/O Bus Bus supports all DMA enabled devices Each transfer uses bus once DMA to memory CPU is suspended once Reduce the number of I/O interfaces in DMA module &

easy to expand