Important Bits and Answers for CSC

- baapek

 The OR gate can be converted to the NAND function by adding----gate(s)to the input of the OR gate. a) NOT b) AND c) NOR d) XOR

 For 1MB memory, the number of address lines required a)12 b)16 c)20 d)32 There is a circuit using 3 nand gates with 2 inputes and 1 output,f ind the output. a) AND b) OR c) XOR d) NAND

 .what is done for push operation a) SP is incremented and then the value is stored. b) PC is incremented and then the value is stored. c) PC is decremented and then the value is stored. d) SP is decremented and then the value is stored.

 Memory allocation of variables declared in a program is ----- a) Allocated in RAM b) Allocated in ROM c) Allocated in stack d) Assigned in registers.

 purpose of PC (program counter)in a microprocessor is --- a) To store address of TOS(top of stack) b) To store address of next instructions to be executed c) count the number of instructions d) to store the base address of the stack.

 In 8085 which is called as High order / Low order Register? Flag is called as Low order register & Accumulator is called as High order Register.

 What happens when HLT instruction is executed in processor? The Micro Processor enters into Halt-State and the buses are tri-stated. Stack pointer is a special purpose 16-bit register in the Microprocessor, which holds the address of the top of the stack.

 Which interrupt is not level-sensitive in 8085? RST 7.5 is a raising edge-triggering interrupt.
In 8085 ,three RST pins are available, such as RST 7.5 ,RST 6.5 , RST 5.5. RST represents Restart Interrupts. These are vectored interrupts that transfer the program control to specific memory locations. They have higher priorities than the INTR interrupt. Among these three, the priority order is 7.5,6.5,5.5.

 conditional results after execution of an instruction in a microprocess is stored in a) register b) accumulator c) flag register d) flag register part of PSW (program status word)

 In 8051microcontroller ,-----has a dual function. a) port 3 b) port 2 c) port 1 d) port 0

 What are Hardware interrupts? - TRAP, RST7.5, RST6.5, RST5.5, INTR. Which interrupt has the highest priority? - TRAP has the highest priority.

What is clock frequency for 8085? 3 MHz is the maximum clock frequency for 8085.

 A positive going pulse which is always generated when 8085 MPU begins the machine cycle. a) RD b) ALE c) WR d) HOLD when a ----- instruction of 8085 MPU is fetched , its second and third bytes are placed in the W and Z registers. a) JMP b) STA c) CALL d) XCHG

 what is defined as one subdivision of the operation performed in one clock period. a) T- State b) Instruction Cycle c) Machine Cycle d) All of the above

 At the end of the following code, what is the status of the flags. LXI B, AEC4H MOV A,C ADD B HLT a) S = 1, CY = 0, P = 0 , AC = 1 b) S =0 , CY = 1, P = 0,AC = 1 c) S = 0, CY = 1, P = 0 , AC = 1 d) S = 0, CY = 1, P = 1 , AC = 1

 The repeated execution of a loop of code while waiting for an event to occur is called ---------.The cpu is not engaged in any real productive activity during this period,and the process doesnt progress towards completion.

a) dead lock b) busy waiting c) trap door d) none.

 microprocessor is ---a) To store address of TOS(top of stack) b) To store address of next instructions to be executed c) count the number of instructions d) to store the base address of the stack.

 conditional results after execution of an instruction in a microprocess is stored in a) register b) accumulator c) flag register d) flag register part of PSW (program status word)

 In 8085 MPU what will be the status of the flag after the execution of the following chunk of code. MVI B,FFH MOV A,B CMA HLT a)S = 1, Z = 0, CY = 1 b)S = 0, Z = 1, CY = 0 c) S = 1, Z = 0, CY = 0 d)S = 1, Z = 1 ,CY = 1

 which of the following instruction is used to load 2050h address toHL register pair? a.LOD H 2050H B.LOAD H 2050H C.LXIH 2050H D.LDAH 2050H

 .what will be the value of the accumalator having AAH after executing RLC instruction twice? a.55h b.abh c.bah d.aah

List the branch related addressing mode: Intra segment Direct Intra segment Indirect Inter segment Direct Inter Segment Indirect

 List the functions of Bus Interface Unit in 8086. Sends out addresses Fetches instructions from memory Reads data from ports and memory Writes data to port and memory

 Write any two advantages of segment registers in 8086 a. It allows the memory capacity to be 1MB even though the address associated with individual instructions are 16 bits wide. b. It allows the instruction,data, or stack portion of a program to be more than 64KB long by using more than one code, data, or stack segment

 Define Inter segment addressing mode: It replaces the contents of IP with part of the instruction and the contents of CS with another part of the instruction.

Define XLAT instruction used in 8086.

It translates a byte in AL using a table in memory. The offset address is calculated by adding the 8 bit contents of the AL register and the contents of BX register. BX register contains the starting offset address of the Lookup table. After execution , corresponding data memory contents of the lookup table are loaded into the AL register.

 What is difference between DIV and IDIV instruction in 8086 ? DIV : It operates only on unsigned number. IDIV : It operates only on signed numbers.

 What is the value of AL after executing the following instructions. MOV AL,35H ADD AL,49H DAA Ans : AL= 84

 Define LAHF and SAHF instructions in 8086. LAHF : Load the 8085 equivalent flags into the AH register. SAHF: Store the AH register into the low order byte of the flag register.