8086 Microprocessor

16 bit microprocessor
16 bit data bus 20 bit address bus 1 Mega byte memory

8086 Architecture

CPU- divided into 2 units 1. BIU 2. EU Work divided among two units Speed Processing

8086 Architecture Contd.

BIU
Circuit for physical address calculation Pre decoding instruction byte queue (6 bytes long) Establish communication with external devices and peripherals

EU
Contains the register set of 8086 16 bit ALU 16 bit flag register Decoding unit which decodes the opcode byte queue issued from instruction byte queue. Timing and control unit Pass results to BIU to be stored in memory
8086 Architecture

Memory Segmentation
1 Mega byte memory is divided into 16 logical segments Each segment 64K bytes in size There are four segments 1. Code segment 2. Data segment 3. Stack segment 4. Extra segment CS-executable program DS, ES-data SS - stack

Physical Address
20 bit physical address is calculated from 2 parts 1.Segment address 2. offset Segment registers-16 bit base address Pointers/Index registers offset CS,DS,SS,ES contain address for code, data and stack segments

Physical Address (Contd.)

20 bit physical address generated from 16 bit base address and 16 bit offset Segment Address-1005H Offset Address- 5555H Segment Address- 0001 0000 0000 0101 Shifted by 4 bit positions0001 0000 0000 0101 0000 Offset Address0101 0101 0101 0101 Physical address0001 0101 0101 1010 0101
1 5 5 A 5

Physical Address (Contd.)

Segment register-Base address of a segment Offset-Distance of required address from base

Offset IP, SI,DI,SP,BP

Memory Segmentation Advantages

memory capacity- 1Mega byte , handling 16 bit addresses Separate segments for code, data and stack Permits program and / or data to be put to different areas Segments can be overlapping / non overlapping

Memory
Memory 8 bits Reads 16 bits from odd addressed byte and even addressed byte (512 KB) If a word begins at even address it is fetch in single fetch cycle If a word begins in odd address it is fetch in two cycles

Register Organization of 8085

General data registers: AH, AL- AX; BH, BL- BX; CH,CL-CX; DH,DL DX AX- Accumulator Segment registers: CS, DS, ES, SS Pointers and Index Registers: IP, SP, BP, SI, DI Offset of code-IP; Offset of stack-SP,BP; SI-offset of source data in DS; DI- offset of destination data in extra segment

Register Organization of 8085

Flag register 16 bit, to indicate the results of computation of ALU
x x x x O D I T S Z x AC x P x CY

O-Overflow flag-Set if overflow occurs S- Sign Flag- Set if result of computation is negative Z- Zero Flag- Result of computation is zero

Register Organization of 8085

P- Parity Flag- Lower byte of result has even number of 1 C- Carry Flag- carry out of MSB in addition or borrow in case of subtraction T- Trap Flag-Processor enters single step mode I-Interrupt Flag- Maskable interrupts are recognized if set D-Direction Flag- Used by string manipulation instructions AC-Auxilliary Carry- Set if there is carry from lower nibble.

Pipelined Architecture
Overlapped fetch and execution cycles Instruction pipelining-Fetched instruction is executed internally, external bus used to fetch next instruction Increases the speed of processor Slow memory parts can be used without affecting overall performance 8086-Implemented using two functional blocksEU and BIU

Signal Description of 8086

Signal Description of 8086

AD0/AD15-Multiplexed data and address bus A19/S6,A18/S5,A17/S4,A16/S3- Multiplexed address and status signals S6-always low and address bit is separated from status bit S5-status of interrupt flag displayed S4 S3-0 0-ES; 0 1-SS; 1 0-CS; 1 1-DS BHE/S7- Outputs BHE signal during first part of bus cycle and S7 on the latter part.

Signal Description of 8086

BHE A0- 0 0- Whole word ; 0 1 Upper byte from or to odd address; 1 0- lower byte from or to even address; 1 1- None RD- Memory/IO read READY- Interfacing with slower peripherals INTR Maskable Interrupt Request TEST- Used along with WAIT signal in multiprocessor environment NMI- Non Maskable Interrupt Request RESET- Terminates activity.

Signal Description of 8086

Clk- Clock Input Vcc- +5 V Supply Gnd- Ground MN/MX- Minimum mode/ Maximum Mode M/IO memory/ IO access INTA Interrupt Acknowledge ALE- Address Latch Enable DT/R Direction of data flow ; Transmit/Receive DEN- Data Enable availability of data

Signal Description of 8086

HOLD/HLDA- Used along with DMA S2, S1, S0 Status lines which indicate type of operation 0 0 0 Interrupt Acknowledge 0 0 1- read I/O Port 0 1 0- write I/O Port 0 1 1 Halt 1 0 0 Code Access 1 0 1 Read memory 1 1 0 Write memory

Signal Description of 8086

LOCK All other system masters will be prevented from gaining system bus control QS1-QS0- Queue Status Information about code- pre fetch queue 0 0 No operation 0 1 First byte of opcode from queue 1 0 Empty queue 1 1 Subsequent byte from queue

Signal Description of 8086

RQ0/ GT0, RQ1/ GT1 Local Bus priority Control Used by other local bus masters in maximum mode to force the processor to release the local bus at the end of processors current bus cycle

Addressing Modes
Way by which operand is specified Addressing mode Data related addressing mode Branch related addressing mode General Instruction format Opcode operand

Data related addressing mode

Immediate 8/16 bit data part of instruction MOV AX, 1000 H Direct- 16 bit EA of datum part of instruction MOV AX, [5000H] Register- Datum stored in register MOV AX, BX (All registers except IP can be used)

Data related addressing

Register Indirect- Offset address of data in BX, SI, DI. Default segment DS,ES MOV AX, [BX] Register Relative- EA of the data formed by adding 8/16 bit offset with the content of BX, BP, SI,DI MOV AX, 50H[BX]. Default segment DS,ES

Data related addressing

Based Indexed- EA obtained from adding contents of base register(BX,BP) and index register (SI,DI) MOV AX, [BX][SI] Relative Based Indexed Addressing- EA obtained from adding contents of adding contents of and 8/16 bit offset. MOV AX, 50H [BX][SI]

Branch Related Addressing Mode

Intrasegment Direct-Address to which control is transferred lies in same segment of the control transfer instruction. Displacement computed relative to IP and given 8/ 16 bit JMP SHORT LABEL Intrasegment Indirect- Displacement in the same segment but passed through indirect mode JMP [BX]

Branch Related Addressing Mode

Intersegment Direct- address to which control is transferred is in different segment. Jump from one code segment to another code segment. CS and IP of the destination address specified directly in the instruction JMP 5000H : 2000H;EA 2000, CS 5000 Intersegment Indirect: address to which control is transferred is in different segment and specified indirectly in the instruction

Instruction Set of 8086

Data Transfer Instructions Arithmetic Instructions Logical Instructions Bit Manipulation Instruction String Instruction Program Execution Transfer Instruction Processor Control Instructions

Data Transfer Instructions

MOV- Copy a word/byte from specified source to specified destination MOV AX, 5000H-Immediate MOV AX,BX-Register MOV AX,[SI]-Indirect MOV AX,[2000H]-Direct MOV AX, 50H[BX]-Based relative MOV DS, 5000H-invalid MOV AX,5000H MOV DS,AX

Data Transfer Instructions

PUSH-Copy specified word to top of stack PUSH AX AH - SP-1 ,AL- SP-2, SP-SP-2 POP-Copy word from top of stack to specified location POP AX SP-AL,SP+1-AH,SP-SP+2 XCHG-Exchange bytes/words XCHG AX,BX XCHG [5000H],AX

Data Transfer Instructions

IN -Copy a byte/word from specified port to accumulator IN AL,03H IN AX,DX OUT- Copy a byte/word from accumulator to specified port OUT 03H,AL OUT DX,AX DX is the only register that hold the 16 bit port address

Data Transfer Instructions

XLAT- Translate a byte in AL using a table in memory MOV AX, SEG TABLE MOV DS,AX MOV AL,CODE MOV BX, OFFSET TABLE XLAT

Data Transfer Instructions

LEA- Load EA to register LEA BX,ADR LEA SI,ADR[BX] LDS/LES-Load Pointer to DS/ES LDS BX,[5000H] BL-5000,BH-5001,DS-5002,5003 LAHF-Loads the AH register with the lower byte of flag register SAHF-Store AH to lower byte of flag register PUSHF-Pushes flag register to stack POPF-Loads the flag register with the contents of memory

Arithmetic Instruction
This instructions affect the conditional flags ADD-Add ADD AX,0100H ADC-Add with carry ADC AX,BX INC-Increment specified byte/word by one INC [BX] DEC-Decrement DEC [5000H] CY not affected

Arithmetic Instruction
SUB-Subtract SUB [5000H], 0100 SBB-Subtract with borrow SBB AX,BX CMP-Compare two specified bytes/words CMP BX,0100H AAA-ASCII Adjust after addition AAS- ASCII adjust after subtraction AAM-ASCII adjust after multiplication AAD-ASCII adjust after division

Arithmetic Instruction
DAA-Decimal Adjust Accumulator DAS-Decimal Adjust after Subtraction NEG-Negate Form 2s compliment of destination MUL-Unsigned multiplication MUL BH (AX) (AL) (BH) MUL CX (DX)(AX) (CX) (AX) IMUL-Signed Multiplication IMUL BH

Arithmetic Instruction
CBW-Convert signed byte to word Byte in AL. Result in AX CWD-Convert signed word to double word. Double word in DX and AX. DIV- Unsigned Division Dividend in AX and divisor specified using any addressing mode except immediate. Result AL(quotient) AH (remainder) DX and AX in case of double word IDIV-signed division.

Logical Instruction
AND-Bit by bit AND AND AX,0005H OR-Logical OR OR AX,BX NOT- Logical Invert NOT [5000H] XOR Logical Exclusive OR XOR AX, [5000H] TEST Logical Compare Instruction TEST AX,BX

Logical Instruction
SHL/SAL-Shift Logical/Arithmetic Left through CY. Count specified by CL SHR/SAR-Shift Logical/Arithmetic Right through CY. Count specified by CL ROR-Rotate right without carry ROL-Rotate left without carry RCR-Rotate right through carry RCL-Rotate left through carry

String Instruction
REP-Repeat Instruction Prefix The instruction is repeated till CX becomes zero REPE/REPZ-Repeat if equal, Repeat if zero REPNE/REPNZ-Repeat if not eqaul and repeat if not zero MOVSB/MOVSW-Moves a string of bytes/words pointed by DS:SI to memory location pointed by ES:DI. Index registers automatically updated depending on DF. Can be used with REP prefix.

String Instruction
CMPS- Compare string byte/word DS:SI and ES:DI point to two strings. The result of comparison on the flags. REP prefix can be used to repeat process. SCAS-Scan string byte/word Scans a string of bytes or words for an operand byte or word specified in AL/AX. String pointed by ES:DI. When a match is found ZF set.

String Instruction
LODS- Load String byte/word Loads AL/AX register by the content of a string pointed by DS:SI. STOS-Store string byte/word Stores the AL/AX register contents to a location in the string pointed by ES:DI.

Control Transfer/Branching Instructions

CALL-Unconditional Call In the case of NEAR CALL IP contents are pushed to stack and in case of FAR CALL, both IP and CS contents are pushed onto stack. Direct Near OPCODE 8/16 bit displacement Indirect Near OPCODE indirect mode Direct Far OPCODE OFFSET CODE Indirect Far OPCODE indirect mode

Control Transfer/Branching Instructions

RET- Return from procedure In case of FAR procedure SP points to IP and CS at time of return. For NEAR procedures SP points to IP only. INT N-Interrupt type N IP of ISS - (N*4); CS of ISS-0000H INT 20H IP-0080 CS-0000 INTO-Interrupt on overflow

Control Transfer/Branching Instructions

JMP-Unconditional Jump IRET-Return from ISR LOOP-Loop unconditionally Loop executed CX number of times Conditional Branching Instructions JZ/JE Label; ZF=1 JNZ/JNE Label; ZF=0 JS; SF=1 JNS Label; SF=0

Control Transfer/Branching Instructions

JP/JPE Label; PF=1 JNP / JPO Label; PF=0 JO Label; OF=1 JNO Label; OF=0 JB/JNAE/JC Label; CF=1 JNB/JAE/JNC Label; CF=0 JBE/JNA Label; CF or ZF=1 JNBE/JA Label; CF or ZF=0 JL/JNGE Label; neither SF=1 nor OF=1

Control Transfer/Branching Instructions

JNL/JGE Label; neither SF=0 nor OF=0 JLE/JNG Label; ZF=1 or neither SF nor OF=1 JNLE/JE Label; ZF=0 or at least any one of SF and OF are not 0 If test condition is met execution branched to label otherwise the program continues its sequence.

Control Transfer/Branching Instructions

LOOPZ/LOOPE Label ZF=1 and CX0 LOOPNZ/LOOPENE Label ZF=0, CX0

Flag Manipulation Instructions

CLC- Clear carry flag CMC-Compliment carry flag STC- Set carry flag CLD-Clear direction flag STD-Set direction flag CLI-Clear Interrupt flag STI-Set interrupt flag

Processor Control Instructions

WAIT- wait for TEST input to go low HLT-Halt the processor NOP- No operation ESC- Escape to external devices like NDP LOCK-Bus lock instruction prefix

Assembler Directives
Directives indicate how an operand section of a program is to be processed by the assembler. DB- Define byte; Reserve bytes of memory locations DW- Define word; Reserve words of memory locations DD-Define double word; Reserve 2 words DQ- Define quad word; Reserve 4 words DT- Define ten bytes; Reserve 10 bytes

Assembler Directives
ASSUME-Assume logical segment name END-End of program ENDP-End of procedure ENDS- End of segment EQU-Assign a label with a value EXTRN- External and Public Indicates that the names, procedures and labels declared after this directive have already been declared in some other modules.

Assembler Directives
FAR- defines a far pointer NEAR-defines a near pointer MACRO-Designates the start of a macro sequence OFFSET- Specifies an Offset address ORG-Sets the origin within a segment PROC- starts procedure PTR-designates a pointer SEGMENT-starts a segment

Assembler Directive
STRUC- defines the start of a data structure Structure name STRUC Sequence of DB,DW and DD directives Structure name ENDS RECORD-This is for defining a bit pattern within a byte or word Record Name RECORD field spec, field spec Field spec-Field name : length= preassignment Pattern RECORD opcode:5,mode:3,opr1:4=8,opr2:4=4;

Assembler Directive
WORD- Indicates word sized EXIT-return to DOS SMALL- only one data segment be used with one code segment EVEN- Forces the address of next byte to be even 00 01 DUP-Duplication operator 02 ARRAY1 DB 2DUP(0,1,2,?) 00 ARRAY1 01
02 -

Concept of modular Programming

Large application programs are developed by team of programmers Overall problem is divided into number of tasks Assembly language aid the modularization process in 3 ways Allow data to be structured so that they can be readily accessed Enables creating procedures/subroutines Permits sections of codes to be inserted by the appearance of single statement(macro)

Macro
A macro is a group of instruction that perform one task Similar to procedure Procedure accessed via CALL instruction

In macro all instructions defined in the macro are inserted at then point of usage

Interrupts
Interrupts are external signals which interrupt the normal execution of a program 8086 interrupts can come from three sources NMI or INTR-Hardware Interrupt INT N Software Interrupt Interrupt due to an error condition from execution of a instruction

Sequence of operation after an interrupt

Stores the content of Flag register, IP and CS contents onto stack. Executes a indirect far jump to ISS. IRET at the end of ISS returns execution to main program. First 1 Kilobyte memory 00000 H to 003FF H set aside as a table for storing the starting address of interrupt service procedures.

Interrupts
4 bytes required to hold the CS and IP values of each interrupt service procedures. The interrupt vector table holds the address of 256 interrupt procedures. Lowest 5 interrupts are dedicated interrupts Divide by zero Single step NMI Breakpoint Interrupt Overflow Interrupt

Interrupts
Interrupts 5 to 31 are reserved for future expansion Interrupts 32 to 255 are available for user Software interrupt- Type 0 through Type 255 INTR- external signal to interrupt execution of program Priority-Divide error, INT N, INTO-Highest NMI INTR Single step-Lowest

Basic 8086 Configurations

Minimum Mode A processor is in minimum mode when its MN / /MX pin is strapped to +5V.

Minimum Mode

Minimum Mode

Minimum Mode
The address must be latched since it is available only during the first part of the bus cycle. To signal that the address is ready to be latched a 1 is put on pin 25, the address latch enable (ALE) pin. Typically, the latching is accomplished using Intel 8282s. Because 8282 is an 8-bit latch, two of them are needed for 16-bit address and three are needed if a full 20-bit address is used.

Minimum Mode

Minimum Mode
The Intel IC device for implementing the transceiver (driver/receiver) block shown is the 8286 transceiver device. The 8286 contains 16 tristate elements, eight receivers and eight drivers. Therefore, two 8286 is needed to service all of the data lines for an 8086 system.

The third component, other than the processor, that is needed in this mode is an 8284A clock generator.

Minimum Mode

Maximum Mode
A processor is in maximum mode when its MN / /MX pin is grounded. The main difference between minimum and maximum mode configurations is the need for additional circuitry to translate the control signals. It is normally implemented with an Intel 8288 bus controller.

Maximum Mode

Maximum Mode

Maximum Mode

Multiprocessor Configuration
Multiprocessing System-A system which includes two or more components that can execute instructions simultaneously Advantages improves overall cost/system performance processors can be combined to fit the needs of application unnecessary expense due to a centralized system can be avoided

Multiprocessor Configuration
provides room for further expansion since tasks are divided, debugging is easy Maximum mode of 8086 supports multiprocessing 3 basic configurations are configurations are possible Closely coupled configuration Loosely coupled configuration Coprocessor configuration

Closely Coupled Configuration

CPU and external processor share the entire memory, I/O system, bus control logic and clock generator. 8086 is the master/host and supporting processor is slave Supporting processor may act independently

Closely Coupled Configuration

Coprocessor Configuration
Same as closely coupled configuration but the supporting processor is dependant and must interact directly with CPU

Loosely Coupled Configuration

Used for medium sized and large systems Each module may be a system master with 8086 and another processor in closely/ coprocessor configuration Several modules may share system resources Inter processor communication through shared resources Each module may include its own memory and I/O devices which can be accessed through local bus

Loosely Coupled Configuration

8087 Numeric Data Processor

Perform arithmetic operations efficiently .

Handle integer, decimal, and real types of data, with lengths ranging from 2 to 10 bytes.
The instruction set supports addition, subtraction, multiplication and division, square root, exponentiation, taking the tangent and so on.

8087 Numeric Data Processor

Provides simple and effective way to enhance the performance of 8086 based system NDP cannot fetch its own instruction Operates with 8086 system in coprocessor configuration where 8086 is host

8087 Numeric Data Processor

8087 Numeric Data Processor

8087 Numeric Data Processor

The monitor and control logic maintains a 6-byte instruction queue and tracks the instruction execution sequence of the host. If the instruction currently being executed by the host is an ESC instruction, the 8087 decodes the external op code to perform the specified operation and also captures the operand and operand address. Instructions other than ESC instructions are simply ignored by the 8087.

8087 Numeric Data Processor

There are eight data registers which can be accessed either as a stack or randomly relative to the top of the stack. An operand may be popped from this stack or pushed onto it. The top stack element is pointed to by the bits 13, 12 and 11 of the status register.

8087 Numeric Data Processor

The status register is 16 bits wide. It reports various errors, stores the condition code for certain instructions, specifies which register is the top of the stack and indicates the busy status. The 16 bit control register provides bits to mask the error interrupts. The remaining bits in the control register provide flexibility in controlling precision (PC), rounding (RC) and infinity representations (IC).

8089 I/O Processor

Handles all system I/O activities Receives request from system peripherals, issues commands to system peripherals and keeps track of operations of peripherals It communicates with the host processor using memory table which contains the details of the task to be executed. Can be connected in closely coupled or loosely coupled configurations

8089 I/O Processor

CPU communicates with the 8089 through memory based blocks which describe the task to be performed The IOP is then interrupted IOP locates the channel program written using 8089 instruction set After execution IOP either interrupts the CPU or update a status location in memory

8086 and 8089 I/O Processor

8089 I/O Processor

This has two internal channels which can be programmed independently Common ALU is shared by both the channels Control unit derives the control signal for the IO channels Bus interface and control unit handles all bus activities Channel Control Pointer (CCP) available for programmers automatically gets loaded with 20 bit address of memory table for channel