I2C interfaces

1he LC2141/2/4/6/8 l2C lnLerfaces are byLe orlenLed and have four operaLlng modes
masLer LransmlLLer mode masLer recelver mode slave LransmlLLer mode and slave recelver mode
ln a glven appllcaLlon Lhe l2C block may operaLe as a masLer a slave or boLh ln Lhe slave mode Lhe l2C hardware
looks for lLs own slave address and Lhe general call address lf one of Lhese addresses ls deLecLed an lnLerrupL ls
requesLed lf Lhe processor wlshes Lo become Lhe bus masLer Lhe hardware walLs unLll Lhe bus ls free before Lhe
masLer mode ls enLered so LhaL a posslble slave operaLlon ls noL lnLerrupLed lf bus arblLraLlon ls losL ln Lhe masLer
mode Lhe l2C block swlLches Lo Lhe slave mode lmmedlaLely and can deLecL lLs own slave address ln Lhe same serlal
Lransfer
aster Transmitter mode
BeIore the master transmitter
mode can be entered, the
I2CONSET register must be
initialized . I2EN must be set to
1 to enable the I2C Iunction. II
the AA bit is 0, the I2C interIace
will not acknowledge any
address when another device is
master oI the bus, so it can not
enter slave mode.
The STA, STO and SI bits must
be 0. The SI Bit is cleared by
writing 1 to the SIC bit in the
I2CONCLR register.
The Iirst byte transmitted
contains the slave address oI the
receiving device (7 bits) and the
data direction bit. In this mode
the data direction bit (R/W)
should be 0 which means Write.
The Iirst byte transmitted
contains the slave address and
Write bit. Data is transmitted 8
bits at a time. AIter each byte is
transmitted, an acknowledge bit
is received.
START and STOP
conditions are
output to indicate
the beginning and
the end oI a serial
transIer.
aster Transmitter mode
1he l2C lnLerface wlll enLer
masLer LransmlLLer mode when
sofLware seLs Lhe S1A blL
1he l2C loglc wlll send Lhe S1A81
condlLlon as soon as Lhe bus ls
free AfLer Lhe S1A81 condlLlon ls
LransmlLLed Lhe Sl blL ls seL and
Lhe sLaLus code ln Lhe l2S1A1
reglsLer ls 0x08
1hls sLaLus code ls used Lo vecLor
Lo a sLaLe servlce rouLlne whlch
wlll load Lhe slave address and
WrlLe blL Lo Lhe l2uA1 reglsLer
and Lhen clear Lhe Sl blL
Sl ls cleared by wrlLlng a 1 Lo Lhe
SlC blL ln Lhe l2CCnCL8 reglsLer
When Lhe slave address and 8/W
blL have been LransmlLLed and an
acknowledgmenL blL has been
recelved Lhe Sl blL ls seL agaln
and Lhe posslble sLaLus codes now
are 0x18 0x20 or 0x38 for Lhe
masLer mode or 0x68 0x78 or
0x80 lf Lhe slave mode was
enabled (by seLLlng AA Lo 1)
aster Receiver mode
ln Lhe masLer recelver mode daLa ls recelved from a slave
LransmlLLer 1he Lransfer ls lnlLlaLed ln Lhe same way as ln
Lhe masLer LransmlLLer mode
When Lhe S1A81 condlLlon has been LransmlLLed Lhe
lnLerrupL servlce rouLlne musL load Lhe slave address and
Lhe daLa dlrecLlon blL Lo Lhe l2C uaLa reglsLer (l2uA1) and
Lhen clear Lhe Sl blL ln Lhls case Lhe daLa dlrecLlon blL
(8/W) should be 1 Lo lndlcaLe a read
When Lhe slave address and daLa dlrecLlon blL have been
LransmlLLed and an acknowledge blL has been recelved Lhe
Sl blL ls seL and Lhe SLaLus 8eglsLer wlll show Lhe sLaLus
code
lor masLer mode Lhe posslble sLaLus codes are 0x40 0x48
or 0x38 lor slave mode Lhe posslble sLaLus codes are 0x68
0x78 or 0x80
aster Receiver mode
$ave Receiver mode
ln Lhe slave recelver mode daLa byLes are
recelved from a masLer LransmlLLer 1o
lnlLlallze Lhe slave recelver mode user
wrlLe Lhe Slave Address reglsLer (l2Au8)
and wrlLe Lhe l2C ConLrol SeL reglsLer
(l2CCnSL1)
l2Ln musL be seL Lo 1 Lo enable Lhe l2C
funcLlon AA blL musL be seL Lo 1 Lo
acknowledge lLs own slave address or Lhe
general call address 1he S1A S1C and Sl
blLs are seL Lo 0
AfLer l2Au8 and l2CCnSL1 are lnlLlallzed
Lhe l2C lnLerface walLs unLll lL ls addressed
by lLs own address or general address
followed by Lhe daLa dlrecLlon blL lf Lhe
dlrecLlon blL ls 0 (W) lL enLers slave
recelver mode lf Lhe dlrecLlon blL ls 1 (8)
lL enLers slave LransmlLLer mode
AfLer Lhe address and dlrecLlon blL have
been recelved Lhe Sl blL ls seL and a valld
sLaLus code can be read from Lhe SLaLus
reglsLer (l2S1A1)
$ave Transmitter mode
1he flrsL byLe ls recelved and handled as ln Lhe slave recelver mode Powever ln Lhls mode Lhe dlrecLlon blL wlll be
1 lndlcaLlng a read operaLlon Serlal daLa ls LransmlLLed vla SuA whlle Lhe serlal clock ls lnpuL Lhrough SCL S1A81
and S1C condlLlons are recognlzed as Lhe beglnnlng and end of a serlal Lransfer
ln a glven appllcaLlon l2C may operaLe as a masLer and as a slave ln Lhe slave mode Lhe l2C hardware looks for lLs
own slave address and Lhe general call address lf one of Lhese addresses ls deLecLed an lnLerrupL ls requesLed
When Lhe mlcroconLrollers wlshes Lo become Lhe bus masLer Lhe hardware walLs unLll Lhe bus ls free before Lhe
masLer mode ls enLered so LhaL a posslble slave acLlon ls noL lnLerrupLed
lf bus arblLraLlon ls losL ln Lhe masLer mode Lhe l2C lnLerface swlLches Lo Lhe slave mode lmmedlaLely and can
deLecL lLs own slave address ln Lhe same serlal Lransfer
I2C seria interface bock diagram
I2C Impementation and operation
Address keg|ster I2ADDk1hls reglsLer may be
loaded wlLh Lhe 7blL slave address (7 mosL
slgnlflcanL blLs) Lo whlch Lhe l2C block wlll
respond when programmed as a slave
LransmlLLer or recelver 1he LS8 (CC) ls used Lo
enable general call address (0x00) recognlLlon
Comparator 1he comparaLor compares Lhe
recelved 7blL slave address wlLh lLs own slave
address (7 mosL slgnlflcanL blLs ln l2Au8) lL also
compares Lhe flrsL recelved 8blL byLe wlLh Lhe
general call address (0x00) lf an equallLy ls found
Lhe approprlaLe sLaLus blLs are seL and an lnLerrupL
ls requesLed
Sh|ft reg|ster I2DA11hls 8blL reglsLer conLalns a
byLe of serlal daLa Lo be LransmlLLed or a byLe whlch
has [usL been recelved uaLa ln l2uA1 ls always
shlfLed from rlghL Lo lefL Lhe flrsL blL Lo be
LransmlLLed ls Lhe MS8 (blL 7) and afLer a byLe has
been recelved Lhe flrsL blL of recelved daLa ls locaLed
aL Lhe MS8 of l2uA1
Whlle daLa ls belng shlfLed ouL daLa on Lhe bus ls
slmulLaneously belng shlfLed ln l2uA1 always conLalns Lhe lasL
byLe presenL on Lhe bus 1hus ln Lhe evenL of losL arblLraLlon
Lhe LranslLlon from masLer LransmlLLer Lo slave recelver ls
made wlLh Lhe correcL daLa ln l2uA1
rbitration and synchronization ogic
ln Lhe masLer LransmlLLer mode Lhe arblLraLlon loglc checks LhaL every LransmlLLed loglc 1 acLually appears as a loglc 1 on Lhe l2Cbus lf anoLher
devlce on Lhe bus overrules a loglc 1 and pulls Lhe SuA llne low arblLraLlon ls losL and Lhe l2C block lmmedlaLely changes from masLer LransmlLLer
Lo slave recelver
1he l2C block wlll conLlnue Lo ouLpuL clock pulses (on SCL) unLll Lransmlsslon of Lhe currenL serlal byLe ls compleLe
ArblLraLlon may also be losL ln Lhe masLer recelver mode Loss of arblLraLlon ln Lhls mode can only occur whlle Lhe l2C block ls reLurnlng a noL
acknowledge (loglc 1) Lo Lhe bus
ArblLraLlon ls losL when anoLher devlce on Lhe bus pulls Lhls slgnal LCW Slnce Lhls can occur only aL Lhe end of a serlal byLe Lhe l2C block generaLes
no furLher clock pulses
$eria cock synchronization
1he synchronlzaLlon loglc wlll
synchronlze Lhe serlal clock
generaLor wlLh Lhe clock pulses on
Lhe SCL llne from anoLher devlce
lf Lwo or more masLer devlces
generaLe clock pulses Lhe mark"
duraLlon ls deLermlned by Lhe devlce
LhaL generaLes Lhe shorLesL marks"
and Lhe space" duraLlon ls
deLermlned by Lhe devlce LhaL
generaLes Lhe longesL spaces"
A slave may sLreLch Lhe space
duraLlon Lo slow down Lhe bus
masLer
1he space duraLlon may also be
sLreLched for handshaklng purposes
1hls can be done afLer each blL or
afLer a compleLe byLe Lransfer
1he l2C block wlll sLreLch Lhe SCL
space duraLlon afLer a byLe has been
LransmlLLed or recelved and Lhe
acknowledge blL has been
Lransferred 1he serlal lnLerrupL flag
(Sl) ls seL and Lhe sLreLchlng
conLlnues unLll Lhe serlal lnLerrupL
flag ls cleared
I2C Impementation and operation
Serlal clock generaLor 1hls programmable clock pulse generaLor provldes Lhe SCL clock pulses when Lhe l2C block ls ln Lhe masLer LransmlLLer or masLer
recelver mode lL ls swlLched off when Lhe l2C block ls ln a slave mode 1he l2C ouLpuL clock frequency and duLy cycle ls programmable vla Lhe l2C Clock
ConLrol 8eglsLers 1he ouLpuL clock pulses have a duLy cycle as programmed unless Lhe bus ls synchronlzlng wlLh oLher SCL clock sources
1lmlng and conLrol 1he Llmlng and conLrol loglc generaLes Lhe Llmlng and conLrol slgnals for serlal byLe handllng 1hls loglc block provldes Lhe shlfL pulses
for l2uA1 enables Lhe comparaLor generaLes and deLecLs sLarL and sLop condlLlons recelves and LransmlLs acknowledge blLs conLrols Lhe masLer and slave
modes conLalns lnLerrupL requesL loglc and monlLors Lhel2Cbus sLaLus
ConLrol reglsLer l2CCnSL1 and l2CCnCL81he l2C conLrol reglsLer conLalns blLs used Lo conLrol Lhe followlng l2C block funcLlons sLarL and resLarL of a serlal
Lransfer LermlnaLlon of a serlal Lransfer blL raLe address recognlLlon and acknowledgmenL
1he conLenLs of Lhe l2C conLrol reglsLer may be read as l2CCnSL1 WrlLlng Lo l2CCnSL1 wlll seL blLs ln Lhe l2C conLrol reglsLer LhaL correspond Lo ones ln Lhe
value wrlLLen Conversely wrlLlng Lo l2CCnCL8 wlll clear blLs ln Lhe l2C conLrol reglsLer LhaL correspond Lo ones ln Lhe value wrlLLen
SLaLus decoder and SLaLus reglsLer 1he sLaLus decoder Lakes all of Lhe lnLernal sLaLus blLs and compresses Lhem lnLo a 3blL code 1hls code ls unlque for
each l2Cbus sLaLus 1he 3blL code may be used Lo generaLe vecLor addresses for fasL processlng of Lhe varlous servlce rouLlnes Lach servlce rouLlne
processes a parLlcular bus sLaLus
1here are 26 posslble bus sLaLes lf all four modes of Lhe l2C block are used 1he 3blL sLaLus code ls laLched lnLo Lhe flve mosL slgnlflcanL blLs of Lhe sLaLus
reglsLer when Lhe serlal lnLerrupL flag ls seL (by hardware) and remalns sLable unLll Lhe lnLerrupL flag ls cleared by sofLware
1he Lhree leasL slgnlflcanL blLs of Lhe sLaLus reglsLer are always zero lf Lhe sLaLus code ls used as a vecLor Lo servlce rouLlnes Lhen Lhe rouLlnes are dlsplaced
by elghL address locaLlons LlghL byLes of code ls sufflclenL for mosL of Lhe servlce rouLlnes
I2C register map
I2C Contro $et register (I2CON$T:
I2C0,I2C0CON$T - 0x001 C000
and I2C1, I2C1CON$T - 0x005 C000)
I2C Contro Cearregister(I2CONCLR:
I2C0,I2C0CONCLR -0x001 C018 and
I2C1, I2C1CONCLR - 0x005 C018)
I2C $tatus register (I2$TT:
I2C0, I2C0$TT - 0x001 C004 and
I2C1,I2C1$TT - 0x005 C004)
1he Lhree leasL slgnlflcanL blLs are always 0 1aken as a byLe Lhe sLaLus
reglsLer conLenLs represenL a sLaLus code 1here are 26 posslble sLaLus
codes When Lhe sLaLus code ls 0xl8 Lhere ls no relevanL lnformaLlon
avallable and Lhe Sl blL ls noL seL All oLher 23 sLaLus codes correspond
Lo deflned l2C sLaLes When any of Lhese sLaLes enLered Lhe Sl blL wlll be
seL
I2C Data register (I2DT:
I2C0, I2C0DT - 0x001 C008 and
I2C1,I2C1DT - 0x005 C008)
1he Cu can read and wrlLe Lo Lhls reglsLer only whlle lL ls noL ln
Lhe process of shlfLlng a byLe when Lhe Sl blL ls seL uaLa ln l2uA1
remalns sLable as long as Lhe Sl blL ls seL
uaLa ln l2uA1 ls always shlfLed from rlghL Lo lefL Lhe flrsL blL Lo be
LransmlLLed ls Lhe MS8 (blL 7) and afLer a byLe has been recelved
Lhe flrsL blL of recelved daLa ls locaLed aL Lhe MS8 of l2uA1
I2C $ave ddress register (I2DR:
I2C0, I2C0DR - 0x001 C00C and
I2C1, I2C1DR - address 0x005 C00C)
1hese reglsLers are readable and wrlLable and ls only used when an
l2C lnLerface ls seL Lo slave mode ln masLer mode Lhls reglsLer has
no effecL 1he LS8 of l2Au8 ls Lhe general call blL When Lhls blL ls
seL Lhe general call address (0x00) ls recognlzed
$eecting the appropriate I2C data rate and duty cyce
SofLware musL seL values for Lhe reglsLers l2SCLP and l2SCLL Lo selecL Lhe approprlaLe daLa raLe and duLy cycle l2SCLP
deflnes Lhe number of CLk cycles for Lhe SCL hlgh Llme l2SCLL deflnes Lhe number of CLk cycles for Lhe SCL low Llme
1he frequency ls deLermlned by Lhe followlng formula (CLk ls Lhe frequency of Lhe perlpheral bus v8)
1he values for l2SCLL and l2SCLP should noL necessarlly be Lhe same
Detais of I2C operating modes
clrcles are used Lo lndlcaLe when Lhe serlal lnLerrupL flag ls seL
1he numbers ln Lhe clrcles show Lhe sLaLus code held ln Lhe l2S1A1 reglsLer AL Lhese polnLs a servlce rouLlne musL be
execuLed Lo conLlnue or compleLe Lhe serlal Lransfer
1hese servlce rouLlnes are noL crlLlcal slnce Lhe serlal Lransfer ls suspended unLll Lhe serlal lnLerrupL flag ls cleared by
sofLware
When a serlal lnLerrupL rouLlne ls enLered Lhe sLaLus code ln l2S1A1 ls used Lo branch Lo Lhe approprlaLe servlce rouLlne lor
each sLaLus code Lhe requlred sofLware acLlon and deLalls of Lhe followlng serlal Lransfer need Lo be undersLood
,aster 1ransm|tter mode
aster Transmitter mode
BeIore the master transmitter mode can be
entered, I2CON must be initialized .
1he l2C raLe musL also be conflgured ln Lhe l2SCLL
and l2SCLP reglsLers
I2EN must be set to logic 1 to enable the I2C block. II the AA
bit is reset, the I2C block will not acknowledge its own slave
address or the general call address in the event oI another device
becoming master oI the bus. In other words, iI AA is reset, the
I2C interIace cannot enter a slave mode.
S1A S1C and Sl musL be reseL
aster Transmitter mode
1he masLer LransmlLLer mode may now be enLered by seLLlng Lhe S1A blL 1he l2C loglc wlll now LesL Lhe l2Cbus and
generaLe a sLarL condlLlon as soon as Lhe bus becomes free
When a S1A81 condlLlon ls LransmlLLed Lhe serlal lnLerrupL flag (Sl) ls seL and Lhe sLaLus code ln Lhe sLaLus reglsLer
(l2S1A1) wlll be 0x08 1hls sLaLus code ls used by Lhe lnLerrupL servlce rouLlne Lo enLer Lhe approprlaLe sLaLe servlce
rouLlne LhaL loads l2uA1 wlLh Lhe slave address and Lhe daLa dlrecLlon blL (SLA+W) 1he Sl blL ln l2CCn musL Lhen be
reseL before Lhe serlal Lransfer can conLlnue
When Lhe slave address and Lhe dlrecLlon blL have been LransmlLLed and an acknowledgmenL blL has been recelved Lhe
serlal lnLerrupL flag (Sl) ls seL agaln and a number of sLaLus codes ln l2S1A1 are posslble
1here are 0x18 0x20 or 0x38 for Lhe masLer mode and also 0x68 0x78 or 0x80 lf Lhe slave mode was enabled (AA
loglc 1)
1he approprlaLe acLlon need Lo be Laken for each of Lhese sLaLus codes
aster Transmitter mode
aster Receiver mode
aster Receiver mode
ln Lhe masLer recelver mode a number of daLa byLes are recelved from a slave LransmlLLer
1he Lransfer ls lnlLlallzed as ln Lhe masLer LransmlLLer mode
When Lhe sLarL condlLlon has been LransmlLLed Lhe lnLerrupL servlce rouLlne musL load l2uA1 wlLh Lhe
7blL slave address and Lhe daLa dlrecLlon blL (SLA+8) 1he Sl blL ln l2CCn musL Lhen be cleared before
Lhe serlal Lransfer can conLlnue
When Lhe slave address and Lhe daLa dlrecLlon blL have been LransmlLLed and an acknowledgmenL blL
has been recelved Lhe serlal lnLerrupL flag (Sl) ls seL agaln and a number of sLaLus codes ln l2S1A1 are
posslble
1hese are 0x40 0x48 or 0x38 for Lhe masLer mode and also 0x68 0x78 or 0x80 lf Lhe slave mode was
enabled (AA 1)
1he approprlaLe acLlon need Lo be Laken for each of Lhese sLaLus codes
aster Receiver mode
$ave Receiver mode
$ave Receiver mode
1o lnlLlaLe Lhe slave recelver mode l2Au8 and l2CCn musL be loaded as follows
1he upper 7 blLs are Lhe address Lo whlch Lhe l2C block wlll respond when addressed by a masLer lf
Lhe LS8 (CC) ls seL Lhe l2C block wlll respond Lo Lhe general call address (0x00) oLherwlse lL lgnores
Lhe general call address
1he l2Cbus raLe seLLlngs do noL affecL Lhe l2C block ln Lhe slave mode l2Ln
musL be seL Lo loglc 1 Lo enable Lhe l2C block 1he AA blL musL be seL Lo
enable Lhe l2C block Lo acknowledge lLs own slave address or Lhe general call
address S1A S1C and Sl musL be reseL
$ave Receiver mode
When I2ADR and I2CON have been initialized, the I2C block waits until it is
addressed by its own slave address Iollowed by the data direction bit which
must be '0 (W) Ior the I2C block to operate in the slave receiver mode.
AIter its own slave address and the W bit have been received, the serial
interrupt Ilag (SI) is set and a valid status code can be read Irom I2STAT. This
status code is used to vector to a state service routine.
The appropriate action need to be taken Ior each oI these status codes .
$ave Receiver mode
1he slave recelver mode may also be enLered lf arblLraLlon ls
losL whlle Lhe l2C block ls ln Lhe masLer mode (see sLaLus 0x68
and 0x78)
lf Lhe AA blL ls reseL durlng a Lransfer Lhe l2C block wlll reLurn a
noL acknowledge (loglc 1) Lo SuA afLer Lhe nexL recelved daLa
byLe Whlle AA ls reseL Lhe l2C block does noL respond Lo lLs
own slave address or a general call address
Powever Lhe l2Cbus ls sLlll monlLored and address recognlLlon
may be resumed aL any Llme by seLLlng AA 1hls means LhaL Lhe
AA blL may be used Lo Lemporarlly lsolaLe Lhe l2C block from
Lhe l2Cbus
$ave Receiver mode
$ave Receiver mode
$ave Transmitter mode
$ave Transmitter mode
uaLa Lransfer ls lnlLlallzed as ln Lhe slave recelver mode
When l2Au8 and l2CCn have been lnlLlallzed Lhe l2C block walLs
unLll lL ls addressed by lLs own slave address followed by Lhe daLa
dlrecLlon blL whlch musL be 1" (8) for Lhe l2C block Lo operaLe ln
Lhe slave LransmlLLer mode AfLer lLs own slave address and Lhe 8 blL
have been recelved Lhe serlal lnLerrupL flag (Sl) ls seL and a valld
sLaLus code can be read from l2S1A1
1hls sLaLus code ls used Lo vecLor Lo a sLaLe servlce rouLlne and Lhe
approprlaLe acLlon need Lo be Laken for each of Lhese sLaLus codes
$ave Transmitter mode
1he slave LransmlLLer mode may also be enLered lf arblLraLlon ls losL
whlle Lhe l2C block ls ln Lhe masLer mode (see sLaLe 0x80)
lf Lhe AA blL ls reseL durlng a Lransfer Lhe l2C block wlll LransmlL Lhe lasL
byLe of Lhe Lransfer and enLer sLaLe 0xC0 or 0xC8 1he l2C block ls
swlLched Lo Lhe noL addressed slave mode and wlll lgnore Lhe masLer
recelver lf lL conLlnues Lhe Lransfer 1hus Lhe masLer recelver recelves all
1s as serlal daLa
Whlle AA ls reseL Lhe l2C block does noL respond Lo lLs own slave
address or a general call address Powever Lhe l2Cbus ls sLlll monlLored
and address recognlLlon may be resumed aL any Llme by seLLlng AA 1hls
means LhaL Lhe AA blL may be used Lo Lemporarlly lsolaLe Lhe l2C block
from Lhe l2Cbus
$ave Transmitter mode
isceaneous $tates
I2S1A1 0xI81hls sLaLus code lndlcaLes LhaL no relevanL lnformaLlon ls
avallable because Lhe serlal lnLerrupL flag Sl ls noL yeL seL 1hls occurs
beLween oLher sLaLes and when Lhe l2C block ls noL lnvolved ln a serlal
Lransfer
I2S1A1 0x001hls sLaLus code lndlcaLes LhaL a bus error has occurred
durlng an l2C serlal Lransfer A bus error ls caused when a S1A81 or S1C
condlLlon occurs aL an lllegal poslLlon ln Lhe formaL frame Lxamples of
such lllegal poslLlons are durlng Lhe serlal Lransfer of an address byLe a
daLa byLe or an acknowledge blL
A bus error may also be caused when exLernal lnLerference dlsLurbs Lhe
lnLernal l2C block slgnals When a bus error occurs Sl ls seL 1o recover
from a bus error Lhe S1C flag musL be seL and Sl musL be cleared 1hls
causes Lhe l2C block Lo enLer Lhe noL addressed" slave mode (a deflned
sLaLe) and Lo clear Lhe S1C flag (no oLher blLs ln l2CCn are affecLed)
isceaneous $tates
$ome specia cases
S|mu|taneous repeated S1Ak1 cond|t|ons from two masters A
repeaLed S1A81 condlLlon may be generaLed ln Lhe masLer
LransmlLLer or masLer recelver modes
A speclal case occurs lf anoLher masLer slmulLaneously generaLes a
repeaLed S1A81 condlLlon unLll Lhls occurs arblLraLlon ls noL losL
by elLher masLer slnce Lhey were boLh LransmlLLlng Lhe same daLa
lf Lhe l2C hardware deLecLs a repeaLed S1A81 condlLlon on Lhe l2C
bus before generaLlng a repeaLed S1A81 condlLlon lLself lL wlll
release Lhe bus and no lnLerrupL requesL ls generaLed
lf anoLher masLer frees Lhe bus by generaLlng a S1C condlLlon
Lhe l2C block wlll LransmlL a normal S1A81 condlLlon (sLaLe 0x08)
and a reLry of Lhe LoLal serlal daLa Lransfer can commence
$ome specia cases
Data transfer after |oss of arb|trat|on
Arbitration may be lost in the master transmitter and master receiver modes .
Loss oI arbitration is indicated by the Iollowing states in I2STAT; 0x38,
0x68, 0x78, and 0xB0
lf Lhe S1A flag ln l2CCn ls seL by Lhe rouLlnes whlch servlce
Lhese sLaLes Lhen lf Lhe bus ls free agaln a S1A81 condlLlon
(sLaLe 0x08) ls LransmlLLed wlLhouL lnLervenLlon by Lhe Cu
and a reLry of Lhe LoLal serlal Lransfer can commence
$ome specia cases
Iorced access to the I2Cbusln some appllcaLlons lL may be posslble for an
unconLrolled source Lo cause a bus hangup ln such slLuaLlons Lhe problem
may be caused by lnLerference Lemporary lnLerrupLlon of Lhe bus or a
Lemporary shorLclrculL beLween SuA and SCL
lf an unconLrolled source generaLes a superfluous S1A81 or masks a S1C
condlLlon Lhen Lhe l2Cbus sLays busy lndeflnlLely lf Lhe S1A flag ls seL and
bus access ls noL obLalned wlLhln a reasonable amounL of Llme Lhen a
forced access Lo Lhe l2Cbus ls posslble 1hls ls achleved by seLLlng Lhe S1C
flag whlle Lhe S1A flag ls sLlll seL
no S1C condlLlon ls LransmlLLed 1he l2C hardware behaves as lf a S1C
condlLlon was recelved and ls able Lo LransmlL a S1A81 condlLlon 1he S1C
flag ls cleared by hardware
$ome specia cases
I2Cbus obstructed by a |ow |eve| on SCL or SDA An l2Cbus hangup occurs lf SuA or SCL ls pulled LCW by an unconLrolled
source
lf Lhe SCL llne ls obsLrucLed (pulled LCW) by a devlce on Lhe bus no furLher serlal Lransfer ls posslble and Lhe l2C hardware cannoL
resolve Lhls Lype of problem When Lhls occurs Lhe problem musL be resolved by Lhe devlce LhaL ls pulllng Lhe SCL bus llne LCW
lf Lhe SuA llne ls obsLrucLed by anoLher devlce on Lhe bus (eg a slave devlce ouL of blL synchronlzaLlon) Lhe problem can be
solved by LransmlLLlng addlLlonal clock pulses on Lhe SCL llne
1he l2C hardware LransmlLs addlLlonal clock pulses when Lhe S1A flag ls seL buL no S1A81 condlLlon can be generaLed because Lhe
SuA llne ls pulled LCW whlle Lhe l2Cbus ls consldered free 1he l2C hardware aLLempLs Lo generaLe a S1A81 condlLlon afLer every
Lwo addlLlonal clock pulses on Lhe SCL llne
When Lhe SuA llne ls evenLually released a normal S1A81 condlLlon ls LransmlLLed sLaLe 0x08 ls enLered and Lhe serlal Lransfer
conLlnues
lf a forced bus access occurs or a repeaLed S1A81 condlLlon ls LransmlLLed whlle SuA ls obsLrucLed (pulled LCW) Lhe l2C hardware
performs Lhe same acLlon as descrlbed above
ln each case sLaLe 0x08 ls enLered afLer a successful S1A81 condlLlon ls LransmlLLed and normal serlal Lransfer conLlnues
noLe LhaL Lhe Cu ls noL lnvolved ln solvlng Lhese bus hangup problems
$ome specia cases
us error A bus error occurs when a S1A81 or S1C condlLlon ls presenL aL an
lllegal poslLlon ln Lhe formaL frame Lxamples of lllegal poslLlons are durlng Lhe
serlal Lransfer of an address byLe a daLa blL or an acknowledge blL
1he l2C hardware only reacLs Lo a bus error when lL ls lnvolved ln a serlal Lransfer
elLher as a masLer or an addressed slave
When a bus error ls deLecLed Lhe l2C block lmmedlaLely swlLches Lo Lhe noL
addressed slave mode releases Lhe SuA and SCL llnes seLs Lhe lnLerrupL flag and
loads Lhe sLaLus reglsLer wlLh 0x00
1hls sLaLus code may be used Lo vecLor Lo a sLaLe servlce rouLlne whlch elLher
aLLempLs Lhe aborLed serlal Lransfer agaln or slmply recovers from Lhe error
condlLlon
$ome specia cases
I2C $tate service routines
I2C State serv|ce rout|nes 1hls secLlon provldes examples of operaLlons LhaL
musL be performed by varlous l2C sLaLe servlce rouLlnes 1hls lncludes
In|t|a||zat|on of the I2C b|ock after a keset I2C Interrupt Serv|ce 1he 26
state serv|ce rout|nes prov|d|ng support for a|| four I2C operat|ng modes
I2C |nterrupt serv|ce When Lhe l2C lnLerrupL ls enLered l2S1A1 conLalns a
sLaLus code whlch ldenLlfles one of Lhe 26 sLaLe servlces Lo be execuLed
1he State serv|ce rout|nes Lach sLaLe rouLlne ls parL of Lhe l2C lnLerrupL
rouLlne and handles one of Lhe 26 sLaLes