Introduction to HDLs

Jayaraj U Kidav Scientist C VLSI Design Group, DOEACC(CEDTI) Calicut

Hardware Description Language

HDL is any language from a class of computer languages and/or programming languages for formal description of electronic circuits. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. HDLs are used to write executable specifications of some piece of hardware.
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Design process of a digital system

Design process of a digital system has 4 phases - Requirement Analysis & Specification. - Design . - Implementation & Testing. - Manufacturing . In 1st phase, Function, Performance and interface requirements are determined and specified.

Design process of a digital system..

In 2nd phase , system is partitioned into different levels of

decomposition such as
- System Design : System is decomposed several subsystems and the communication protocol among them is also defined. - Architectural Design : Architectural style and performance

of each subsystem is determined.

Design process of a digital system

RTL Design : Architecture is translated into an interconnection of RTL Modules. - Logic design: RTL Modules are constructed using logic gates. In 3rd phase, subsystems are implemented and tested including partitioning, placement and routing to produce a layout of circuit. In final phase , process is to prototype , manufacture the design.

HDLs - Motivation
Increased productivity shorter development cycles, more features, but........still shorter time-tomarket, 10-20K gates/day/engineer Flexible modeling capabilities. can represent designs of gates or systems description can be very abstract or very structural
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 Design reuse is enabled. packages, libraries, support reusable, portable code Design changes are fast and easily done convert a 8-bit register to 64-bits........four key strokes, and its done! exploration of alternative architectures can be done quickly
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 Use of various design methodologies. top-down, bottom-up, complexity hiding (abstraction) Technology and vendor independence. same code can be targeted to CMOS, ECL, GaAs same code for: TI, NEC, LSI, TMSC same code for: .5um, .35um, .25um, .18um

 Enables use of logic synthesis which allows a investigation of the area and timing space. Using a standard language promotes clear communication of ideas and designs.

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Do We Really Need HDLs ??

Before Emergence of HDLs How was Designing Field ??

We where designing systems using Boolean equationsisn't ?

Schematic representation

Drawbacks of traditional Designing methods

System will be specified as interconnected blocks and this is not how specification of system is given to you or created. System spec is always given as behavior of a system. Handling of large complex system is not feasible. Analyzing thousands of Boolean equations is not possible. We all know that over six thousand gates the schematic become incomprehensible. We in modern world deal with millions of gates.

So We go for HDLs
What are these HDLs ??

Hardware Description Language.

What they do ?? Describe digital circuits. HDLs allowed the designers to model the concurrency of processes found in hardware elements. HDLs such as Verilog HDL and VHDL became popular.

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Comparison b/w Traditional approach and HDL approach.

Sreejeesh S.G

ORIGIN OF VHDL
Initiated by US Governments Dept of Defense VHSIC Program in 1980. IBM, TI and Intermetrics started the development of VHDL in 1983 VHDL Ver. 7.2 released in 1985.

IEEE standard 1076-1987 in 1987.

IEEE 1076-1993 - revision in 1993

VHDL

Very High Speed Integrated Circuit Hardware

Description Language
VHDL is an industry standard HDL for the Description, Modeling and Synthesis of digital circuits and systems.

VHDL
It is the most popular HDL , worldwide. System specification can be done structural or/and in behavioral levels. Good VHDL simulation tools are available in market at reasonable price. Synthesis with VHDL is available with all most all EDA vendors. It is a universal modeling language, i.e. it can be used to model electromechanical systems, hydraulics, chemical and other system. It is not restricted only to electronics.

BASIC FEATURES OF VHDL

CONCURRENCY. SUPPORTS SEQUENTIAL STATEMENTS. SUPPORTS FOR TEST & SIMULATION. STRONGLY TYPED LANGUAGE. SUPPORTS HIERARCHIES. SUPPORTS FOR VENDOR DEFINED LIBRARIES. SUPPORTS MULTIVALUED LOGIC.

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CONCURRENCY
VHDL is a concurrent language. HDL differs with Software languages with respect to Concurrency only. VHDL executes statements at the same time in parallel, as in Hardware.

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Advantages of VHDL
Can verify design functionality early in the design process and simulate a design written as a VHDL description. Logic Synthesis and optimization converts a VHDL description to a gate level implementation in a given technology.

Reduces circuit design time and errors.

VHDL descriptions provide technology independent documentation for a design and its functionality.

Advantages of VHDL..
Powerful constructs to write complex logic.

It has multiples levels of design descriptions.

It supports design libraries and the creation of

reusable components.

It provides for design hierarchies to create module

design.

Advantages of VHDL.
Device independent design

VHDL permits to create a design without first choosing the device for implementation
Portability

VHDL is an IEEE standard. Libraries of VHDL models of components can be shared across platforms, tools organization and technical group
ASIC Migration Quick time to market and low cost

Capabilities
VHDL supports design hierarchies A digital system can be modeled as a set of interconnected components It supports flexible design methodologies Top-down , Bottom-up or mixed. VHDL is not technology specific. It can support various hardware technologies It supports both synchronous and asynchronous timing models

Capabilities
Various modeling techniques such as FSM, algorithmic and Boolean equations can be modeled using VHDL. Any large design can be modeled using VHDL

No limitation imposed by the size of a design

Test benches can be written in VHDL to test other models.

Capabilities
Propagation delays, set-up and hold time timing constraints can be described in VHDL Generics and attributes are useful in describing parameterized design

Models written in VHDL can be verified by Simulation

Behavioral models are capable of being synthesized to gate- level description

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Disadvantages
Less control of defining gate level implementation.

The implementation created by synthesis tool is

inefficient. The quality of synthesis varies from tool to tool.

Summary
VHDL modeling can be used to model hardware at multiples levels of abstraction. VHDL is independent of technology and design methodologies and promotes portable descriptions, rapid prototyping and free exchange of models among organizations and individuals.

Any Questions ??

Thanks.