Overview

 VHDL Processes
 If-Then-Else and CASE statements
 Flip-Flop description using VHDL
 Sequential circuit description (state
tables and diagrams) using VHDL
 Process synchronization

Oct 23, 2008 MKM - 1

 VHDL Process
 A group of VHDL statements that are
“executed” when one signal in a specified
group changes.
 Many processes can be executed
concurrently.
 “Body” of process implements a sequential
program, i.e. signal values are updated only
when the process completes.
 Can also use variables, whose value is
updated immediately.
Oct 23, 2008 MKM - 2
VHDL Architecture Structure
architecture name_arch of name is
Signal assignments
begin
Concurrent statements Processes contain sequential
statements, but execute
Process 1 concurrently within the
architecture body
Concurrent statements

Process 2

Concurrent statements

end name_arch;
Oct 23, 2008 MKM - 3
 VHDL Process Syntax
Signals and/or
Variables

P1: process (<sensitivity list>)

<variable declarations>
begin
<sequential statements>
end process P1;
Optional process label
Within a process:
Variables are assigned using :=
and are updated immediately.
Signals are assigned using <=
and are updated at the end of
the process.

Oct 23, 2008 MKM - 4

Signals Vs Variables in a Process
Let A, B, and C be integer data types with
A=1, B=5, and C=10.
A, B, C: signals A, B, C: variables
begin process begin process
… …
B <= A; B := A;
C <= B; C := B;
… …
end process; end process;
B = 1 and C = 5 B = 1 and C = 1
( uses original value ( uses new value
B (=5) when of B (=1) when
computing C ) computing C )

Oct 23, 2008 MKM - 5

 Methodology

RASSP
VHDL Sequential Statements
Reinventing
Electronic
Design
Architecture Infrastructure

DARPA Tri-Service

● Assignments executed sequentially in processes

● Sequential statements
❍ {Signal, variable} assignments
❍ Flow control
❑ IF <condition> THEN <statements> [ELSIF <statements]
[ELSE <statements>] END IF;
❑ FOR <range> LOOP <statements> END LOOP;
❑ WHILE <condition> LOOP <statements> END LOOP;
❑ CASE <condition> IS WHEN <value> => <statements>
{WHEN <value> => <statements>}
[WHEN others => <statements>]
END CASE;
❍ WAIT [ON <signal>] [UNTIL <expression>] [FOR <time>] ;
❍ ASSERT <condition> [REPORT <string>] [SEVERITY <level>] ;
Copyright  1995-1999 SCRA

Oct 23, 2008 MKM - 6

Combinational circuit description
using a VHDL process

Remember the n-line 4 x 1 multiplexer:

Sel y
a(n-1:0) “00” a
8-line
b(n-1 :0) “01” b
4x1 y(n-1 :0)
c(n-1 :0) MUX “10” c
d(n-1 :0) “11” d

sel(1:0)

Oct 23, 2008 MKM - 7

 An n-line 4 x 1 multiplexer:
using a CASE statement
architecture mux4g_arch of mux4g is
begin
process (sel, a, b, c, d) Sel y
begin
“00” a
case sel is
when "00" => y <= a; “01” b
when "01" => y <= b; “10” c
when "10" => y <= c; “11” d
when others => y <= d;
end case;
end process;
end mux4g_arch; Must include ALL posibilities
in case statement

Oct 23, 2008 MKM - 8

 If-Then-Else statement
[ if_label:]
if boolean_expression then
{ sequential_statement; }
{ elsif boolean_expression then
{ sequential_statement; } }
[ else
{ sequential_statement; } ]
end if [ if_label ];

Notation:
[ ] -- optional
{ } -- repeatable

Oct 23, 2008 MKM - 9

 CASE statement

[ case_label:]
case expression is
{ when choices =>
{ sequential
statement; }
}
end case [case_label];

Oct 23, 2008 MKM - 10

 Methodology

RASSP
The Wait Statement
Reinventing
Electronic
Design
Architecture Infrastructure

DARPA Tri-Service

● The wait statement causes the suspension of a process

statement or a procedure
● wait [sensitivity_clause] [condition_clause] [timeout_clause ] ;
❍ sensitivity_clause ::= ON signal_name { , signal_name }
WAIT ON clock;
❍ condition_clause ::= UNTIL boolean_expression
WAIT UNTIL clock = ‘1’;
❍ timeout_clause ::= FOR time_expression
WAIT FOR 150 ns;

Copyright  1995-1999 SCRA

Oct 23, 2008 MKM - 11

 Methodology

RASSP
Equivalent Processes
Reinventing
Electronic
Design
Architecture Infrastructure

DARPA Tri-Service

● “Sensitivity List” vs “wait on”

Summation:
Summation: Summation:
Summation: PROCESS
PROCESS
PROCESS(
PROCESS( A, A, B,
B, Cin)
Cin) BEGIN
BEGIN
BEGIN
BEGIN
Sum
Sum <=
<= AA XOR
XOR BB XOR
XOR
= Sum
Sum <=
<= AA XOR
XOR BB XOR
WAIT
WAIT ON
XOR Cin;
ON A,
Cin;
A, B,
B, Cin;
Cin;
Cin; END
Cin; END PROCESS
PROCESS Summation;
Summation;
END
END PROCESS
PROCESS Summation;
Summation;

if you put a sensitivity list in a process,

you can’t have a wait statement!

if you put a wait statement in a process,

you can’t have a sensitivity list!

Copyright  1995-1999 SCRA

Oct 23, 2008 MKM - 12

Flip-Flop description using VHDL:
Positive Edge-Triggered D-FF with Reset
 Entity Declaration:
-- Positive Edge-Triggered D Flip-Flop with Reset:
-- VHDL Process Description
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(CLK, RESET, D: in std_logic;
RESET Q
Q, Q_n: out std_logic);
D dff
end dff;
Q_n

CLK

Oct 23, 2008 MKM - 13

Flip-Flop description using VHDL:
Positive Edge-Triggered D-FF with Reset
 Architecture:
architecture pet_pr of dff is
-- Implements positive edge-triggered bit state storage
-- with asynchronous reset.
signal state: std_logic;
begin
Q <= state;
Q_n <= not state; Specifies FF triggering:
process (CLK, RESET) positive edge-trigger
begin RESET Q
if (RESET = '1') then
state <= '0';
D dff
else Q_n
if (CLK'event and CLK = '1') then
state <= D;
end if; CLK
end if;
Q(t+1) = D(t).RESET
end process;
end;
Oct 23, 2008 MKM - 14
 Methodology

RASSP
Inertial vs Transport Delays
Reinventing
Electronic
Design
Architecture Infrastructure

DARPA Tri-Service

Transport Timing
A ENTITY
ENTITY nand2
nand2 IS
IS
C
B PORT(
PORT( A, B :: IN
A, B IN BIT;
BIT; CC :: OUT
OUT BIT);
BIT);
END nand2;
END nand2;

ARCHITECTURE
ARCHITECTURE behavior
behavior OFOF nand2
nand2 IS
IS
BEGIN
BEGIN
CC <=
<= TRANSPORT
TRANSPORT NOT(A
NOT(A AND
AND B)
B)
Inertial Timing AFTER
AFTER 25 ns;
25 ns;
END
END behavior;
behavior;
ENTITY
ENTITY nand2
nand2 IS
IS
PORT(
PORT( A, B :: IN
A, B IN BIT;
BIT; CC :: OUT
OUT
BIT);
BIT);
END
END nand2;
nand2;

ARCHITECTURE
ARCHITECTURE behavior behavior OFOF nand2
nand2 IS
IS
BEGIN
BEGIN
CC <= <= NOT(A
NOT(A AND
AND B)
B) AFTER
AFTER 25
25 ns;
ns;
END
END
Copyright
behavior;
behavior;
 1995-1999 SCRA

Oct 23, 2008 MKM - 15

 INERTIAL DELAY MODEL
 THIS DELAY OFTEN FOUND IN “SWITHCHING CIRCUIT”

 *INPUTS VALUE MUST BE STABLE FOR A SPECIFIED

PULSE REJECTION LIMIT DURATION BEFORE THE
VALUE IS ALLOWED TO PROPAGATE TO THE OUTPUT .

 *IN ADDITION, THE VALUE APPEARS AT THE

OUTPUTAFTER THE SPECIFIED INERTIAL DELAY.

 *IF THE INPUT IS NO STABLE FOR THE SPECIFIED

LIMIT,NO OUTPUT CHANGE OCCURES.

 *WHEN USED WITH SIGNAL ASSIGNMENTS, THE INPUT

VALUE IS REPRESENTED BY THE VALUE OF
EXPRESSION ON THE RIGHT HAND SIDE AND THE
OUTPUT
Oct 23, 2008 IS REPRESENTED BY THE TARGET SIGNAL.
MKM - 16
Oct 23, 2008 MKM - 17
 TRANSPORT DELAY MODEL

 THE DELAYS IN HARDWARE THAT DO NOT

EXHIBIT ANY INERTIAL DELAY.

 *THIS DELAY REPRESENTS PURE PROPAGATION

DELAY, THAT IS ANY CHANGES ON AN INPUTARE
TRANSPORTED TO THE OUTPUT, NO MATTER HOW
SMALL, AFTER THE SPECIFIED DELAY.

Oct 23, 2008 MKM - 18

Oct 23, 2008 MKM - 19
 Methodology

RASSP
Testbenches
Reinventing
Electronic
Design
Architecture Infrastructure

DARPA Tri-Service

● Testbench is the system’s top level component

❍ Its entity declaration does not contain any PORT signals
❍ It instantiates all the necessary components that
comprise the system
● Testbenches may serve three additional useful
purposes:
❍ May generate stimulus for simulation:
❑ Behavioral descriptions can be used to generate
input vectors
❍ May apply stimulus to the entity under test
❑ Locally declared signals can be connected to
PORTS of components in the system
❍ May compare output responses with expected values
❑ Behavioral descriptions can be used to compare
model outputs to expected responses
Copyright  1995-1999 SCRA
Oct 23, 2008 MKM - 20
 EXAMPLE OF TEST BENCH

Oct 23, 2008 MKM - 21

 FINITE STATE MACHINES

Oct 23, 2008 MKM - 22

Definition of a State Machine
 All programmable logic designs can be
specified in Boolean form. However
some designs are easier to
conceptualize and implement using non-
Boolean models. The State Machine
model is one such model.

Oct 23, 2008 MKM - 23

Definition of a State Machine
 A state machine represents a system as
a set of states, the transitions between
them, along with the associated inputs
and outputs.
 So, a state machine is a particular
conceptualization of a particular
sequential circuit. State machines can
be used for many other things beyond
logic design and computer architecture.
Oct 23, 2008 MKM - 24
 Finite State Machines
 Any Circuit with Memory Is a Finite
State Machine
 Even computers can be viewed as huge
FSMs
 Design of FSMs Involves
 Defining states
 Defining transitions between states

 Optimization / minimization

 Above Approach Is Practical for Small

FSMs Only
Oct 23, 2008 MKM - 25
State Machines: Definition of
Terms
State Diagram
Illustrates the form and
function of a state machine.
Usually drawn as a bubble-
and-arrow diagram.
State
A uniquely identifiable set
of values measured at
various points in a digital
system.
Next State
The state to which the
state machine makes the
next transition, determined
by the inputs present when
Oct 23, 2008
the device is clocked.
Branch
A change from present
state to next state.
Mealy Machine
A state machine that
determines its outputs from
the present state and from
the inputs.
Moore Machine
A state machine that
determines its outputs from
the present state only.
MKM - 26
Present State and Next State
State 4 For any given state, there is
a finite number of possible
next states. On each clock
cycle, the state machine
branches to the next state.
One of the possible next
State 5 states becomes the new
present state, depending on
the inputs present on the
clock cycle.
State 6 State 7

 On a well-drawn state diagram, all possible transitions will be

visible, including loops back to the same state. From this diagram
it can be deduced that if the present state is State 5, then the
previous state was either State 4 or 5 and the next state must
Octbe either 5, 6, or 7.
23, 2008 MKM - 27
 Moore and Mealy Machines
 Both these machine types follow the basic
characteristics of state machines, but differ in the
way that outputs are produced.
 Moore Machine:
 Outputs are independent of the inputs, ie outputs
are effectively produced from within the state of
the state machine.
 Mealy Machine:
 Outputs can be determined by the present state
alone, or by the present state and the present
inputs, ie outputs are produced as the machine
makes a transition from one state to another.
Oct 23, 2008 MKM - 28
 Machine Models
Inputs Inputs

Combinatorial Combinatorial
Logic to Logic to
Determine State Determine State

Present State Present State

Register Bank Register Bank

Combinatorial
Combinatorial
Logic to
Logic to
Determine
Determine
Output Based on:
Output Based on:  Present State
 Present State
 Present Inputs
Moore Machine Mealy Machine
Output Output
Oct 23, 2008 MKM - 29
 EXAMPLE

Oct 23, 2008 MKM - 30

Oct 23, 2008 MKM - 31
Oct 23, 2008 MKM - 32
 MEALY MACHINE

Oct 23, 2008 MKM - 33

Oct 23, 2008 MKM - 34
 FSM VHDL Design Example
 0110 sequence
detector, Mealy
machine no pattern
overlapping

Oct 23, 2008 MKM - 35

 0110 Detector Mealy FSM
No overlapping
architecture NOOV of
library IEEE; MEALY0110NV is
use type STATE_TYPE is
IEEE.STD_LOGIC_1164.all (IDLE,S0,S01,S011);
; signal CS,NS: STATE_TYPE;
entity MEALY0110NV is begin
port (CLK,RST,X : in SEQ: process (CLK,RST) is
std_logic; begin
Z : out std_logic); if (rising_edge(CLK)) then
end entity MEALY0110NV; if (RST=‘1’ ) then
CS<=IDLE;
else
CS <= NS;
end if;
end if;
end process SEQ;
Oct 23, 2008 MKM - 36
 0110 Detector Mealy FSM
No overlapping
COM: process (CS,X) is when S01=>
begin if (X = ‘0') then
Z<=‘0’; NS<=S0;
case CS is else
when IDLE => NS<=S011;
if (X = ‘0') then end if;
NS<=S0; when S011 =>
else if (X = ‘0') then
NS<=IDLE; NS<=IDLE;
end if; Z<=‘1’;
when S0 => else
if (X = ‘0') then NS<=IDLE;
NS<=S0; end if;
else end case;
NS<=S01; end process COM;
end if; end architecture NOOV;
Oct 23, 2008 MKM - 37
 0110 Detector Moore FSM No overlapping
Another VHDL code style (three processes)
library IEEE; architecture NOOV of MOORE0110NV
is
use
type STATE_TYPE is
IEEE.STD_LOGIC_1164.all (IDLE,S0,S01,S011,S0110);
;
signal CS,NS: STATE_TYPE;
entity MOORE0110NV is begin
port (CLK,RST,X : in SEQ: process (CLK) is
std_logic; begin
Z : out std_logic); if (rising_edge(CLK)) then
end entity MOORE0110NV; if (RST=‘1’ ) then
CS<=IDLE;
else
CS <= NS;
end if;
end if;
Oct 23, 2008 end process SEQ; MKM - 38
 0110 Detector Moore FSM
No overlapping
COM: process (CS,X) is when S01=>
begin if (X = ‘0') then
case CS is NS<=S0;
else No output Z in
when IDLE =>
NS<=S011; the COM
if (X = ‘0') then
end if;
NS<=S0; process
when S011 =>
else if (X = ‘0') then
NS<=IDLE; NS<=S0110;
end if; else
when S0 => NS<=IDLE;
end if;
if (X = ‘0') then
when S0110=>
NS<=S0;
NS<=IDLE;
else
end case;
NS<=S01; end process COM;
end if;

Oct 23, 2008 MKM - 39

 0110 Detector Moore FSM
No overlapping
OUTPUTZ: process (CS) is
OR
begin Z<=‘1’ when CS=S0110 else
case CS is ‘0’;
when IDLE|S0|S01| end architecture NOOV;
S011=>
Z<=‘0’;
when S0110=>
Z<=‘1’; 3rd process defines the
end case;
output function
end process OUTPUTZ;
end architecture NOOV;

Oct 23, 2008 MKM - 40