Lecture 3

Motivation for HDL and

Levels of Hardware
Abstraction
 Motivation for HDL

• Requirements specification

- First stage in design is the documentation of

system requirements.

- System Requirements: function and performance

- Formal technique via a HDL is desirable.

 Motivation for HDL

• Design documentation and communication

- Due to increased design complexity, a large

number of individuals are involved in design.

- Formal specification via HDL facilitates easier

and error free communication of design.

- Formal documentation also aids in

maintaining legacy systems.
 Motivation for HDL
Facilitates structured designed methodologie

- Aids in design partitioning in

>> space (structural)
>> time (functional)

- Decreases complexity by supporting design

abstraction.

- Supports black box approach with clear distinctio

between functional and interface behavior
 Motivation of HDL

• Design verification via simulation

- The initial requirements specification and actual

design can both be simulated with same test
stimuli.

- Comparison of the resulting outputs verifies the

functionality of the design.
 Motivation of HDL
• Design verification through formal technique

- A formal specification at both requirements and

design level aids in formal verification.

- Formal verification refers to logically proving the

equivalence of two specifications with out actua
simulation.

- This techniques saves time in comparison to

simulation based technique.
 Motivation for HDL

Automated synthesis through computer-aided

design tools

- Computer aided design tools automatically

synthesize or generate the hardware from the
requirement specification.

- Automated synthesis reduces design time and

eliminates errors due to manual design.
 Motivation for HDL

• Unifying Philosophy

- Maximum reliability in design process at

minimum cost and design time.
Traditional Hardware Levels
of Abstraction
St

al
ru

n
Proc. Mem. Switch ct

io
Algorithm
ur

ct
al

n
Fu
Y-Chart

Floorplan
Geometric
 HW Design Abstraction
Structural Functional
P S M loop
for each data input
…..
I/P end;
wait for 10 ms;
O/P end;

Pad Frame
I/P
Geometric P S M

O/P
Traditional Hardware Levels
of Abstraction
St

al
ru

n
Proc. Mem. Switch ct

io
Algorithm
ur

ct
al RT Language

n
RT

Fu
Y-Chart

Standard Cells

Floorplan
Geometric
HW Design Abstraction
Structural Functional
ALU

GPR MAR<- PC, Mem_rd <- 1

Control PC <- PC + 1
Section Wait until ready = 1
Temp IR <- Mem_data
Mem_rd <- 0

IR
PC

MAR

MDR
 Traditional Hardware Levels
of Abstraction
St

al
ru

n
Proc. Mem. Switch ct

io
Algorithm
ur

ct
al RT Language

n
RT

Fu
Gate Boolean Eqn or Truth Tab
Differential Eqn
Y-Chart Transistor
Polygons

Sticks

Standard Cells

Floorplan
Geometric
 Standard Cells

“Principles of CMOS VLSI Design”, Weste and Eshragian

Standard Cell Symbolic
Layout
Standard Cell Symbolic
Layout
Actual Layout
 Traditional Hardware Levels of
Abstraction

Proc. Mem. Switch Algorithm

RT RT Language

Gate Boolean Eqn or Truth Tab

Differential Eqn
Y-Chart Transistor
Polygons

Sticks

Standard Cells

Floorplan
Merging of 3-axis
Algorithm or
Behavioral Level

Structure or
Register Transfer (RT) Level
Levels of
Design
Logic Gates Abstraction

Transistors
Digital System Design

IDEA

Behavioral Design
Algorithm
Structural Design
State machine,ALU,Regs
Logic Design
Gate level netlist
Physical Design
Transistor list
Fabrication

ASIC
Digital System Design

IDEA

Behavioral Design
Behavioral Simulation
Structural Design
Structural Simulation
Logic Design
Gate level Simulation
Physical Design
Device level Simulation
Fabrication
Testing
ASIC
Digital System Design
Specification at
higher level of
abstraction

Verification by
Translation or
Simulation
Design

Specification at
lower level of
abstraction
 Digital System Design

IDEA
SystemC,
Behavioral Design
Celoxica HandelC Compiler,
Forte SystemC Compiler
Structural Design
VHDL, Xilinx ISE Foundation series
Logic Design
VHDL, Xilinx ISE Foundation series
Physical Design

Fabrication

ASIC