Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007

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Hu|t|p||ers and 8h|fters Hu|t|p||ers and 8h|fters
S. Sundar Kumar yer
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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.now|edgement .now|edgement
Slides taken from
http://bwrc.eecs.berkeley.edu/cBook/index.htm
which is the web-site of "Digital ntegrated Circuit A Design
Perspective by Rabaey, Chandrakasan, Nicolic
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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ut||ne ut||ne
ultipliers
Basic Algorithm
Array ultiplier
Carry-Save ultiplier
Wallace-Tree ultiplier
Shifter
Binary Shifter
Barrel Shifter
Logrithmic Shifter
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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Hu|t|p||ers Hu|t|p||ers
xpensive and slow operations
ultiplication units in state of the art DSP and P
Complex adders earlier discussion on adders relevant
Partial products; accumulation; final summation
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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%he |nary Hu|t|p||.at|on %he |nary Hu|t|p||.at|on
Z X

Y - Z
k
2
k
k 0

X
i
2
i
i 0

' '



+
Y
j
2
j
j 0

' '



+

X
i
Y
j
2
i j
j 0

' '



+
i 0

X X
i
2
i
i 0

Y Y
j
2
j
j 0

ith
W ultiplication needs cycles using N-bit adder
W n shift and add
- partial product added
-Partial product is AND operation of multiplier bit
and multiplicand followed by a 'shift'
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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%he |nary Hu|t|p||.at|on %he |nary Hu|t|p||.at|on
x

Partial products
ultiplicand
ultiplier
Result
1 0 1 0 1 0
1 0 1 0 1 0
1 0 1 0 1 0
1 1 1 0 0 1 1 1 0
0 0 0 0 0 0
1 0 1 0 1 0
1 0 1 1
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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!art|a| !rodu.t Cenerat|on !art|a| !rodu.t Cenerat|on
Logical AND of multiplicand and multiplier bit
i
Adding zeros has no impact on results
Can reduce no. or partial products by half!!
g. 0111 1110 = 1000 0010 where 1 = -1
So only two partial products need be added!
(N-1)/2
ultiplier word Y = %

with

1 -2,-1, 0, 1, 2}
=0
This transformation is Booth's Recoding
Leads to less additions with area reduction and higher speed
Alternating 10101010 for eight bit is the worst case!
ultiplying with -2,-1, 0, 1, 2} versus 1, 0}; needs encoding
Used modified Booth's recoding for consistent operation size
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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Hod|f|ed ooth's Re.ord|ng Hod|f|ed ooth's Re.ord|ng
!,7ti, !7oduct Seection T,-e
Mutipie7 Bits Reco7ded Bits
000 0
001 + ultiplicand
010 + ultiplicand
011 +2 ultiplicand
100 -2 multiplicand
101 - ultiplicand
110 - ultiplicand
111 0
WBunch bits from 2sb to lsb in
three with successive overlap
WAssign multiplier as per the table
WNumber of partial products is half
g. 01111111 is bunched into
01(1), 11(1), 11(1), 11(0)
ultiplier = 10 00 00 01
(see table)
Four partial products developed
instead of eight
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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%he rray Hu|t|p||er %he rray Hu|t|p||er

3

2

1

0

3
HA

2
FA

1
FA

0
HA

2
3
FA

2
FA

1
FA

0
HA

7

5

3
FA

2
FA

1
FA

0
HA

0
W partial products of bit size each
W two bit AND; -1 -bit adders
W Layout need not be straggled, but routing will take care of shift
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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%he HxN rray Hu|t|p||er %he HxN rray Hu|t|p||er -- 6r|t|.a| !ath 6r|t|.a| !ath



Critical Path 1
Critical Path 2
Critical Path 1 & 2
any critical paths!! Critical timing determination non-trivial
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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%ransm|ss|on Cate Fu|| dder %ransm|ss|on Cate Fu|| dder
A
B
P
C
i
J
DD
A
A A
J
DD
C
i
A
P
A
B
J
DD
J
DD
C
i
C
i
C
o
S
C
i
P
P
P
P
P
Sum Generation
Carry Generation
Setup
W Similar circuits for sum and carry generation
W t
sum
= t
carry
in this case
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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6arry 6arry--8ave Hu|t|p||er 8ave Hu|t|p||er




'ector erging //er
WCarry passed diagonally downward
WAssumes 9
,dd
= 9
c,77
xtra set of adders
Usually fast carry look ahead adder
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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Hu|t|p||er F|oorp|an Hu|t|p||er F|oorp|an
S C S C S C S C
S C S C S C S C
S C S C S C S C
S
C
S
C
S
C
S
C
Z
0
Z

Z
2
Z
3
Z
4
Z
5
Z
6
Z
7
X
0
X

X
2
X
3
Y

Y
2
Y
3
Y
0
'ector erging Cell
ultiplier Cell
ultiplier Cell
X an/ Y signals are broa/caste/
through the complete array.
( )
W,n m,e ,out 7ect,ngu,7
WRegu,7 sh,pe ,nd ,out
WAmen,-e to ,utom,tion
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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a||a.e a||a.e--%ree Hu|t|p||er %ree Hu|t|p||er
6 5 3 2 1 0 6 5 3 2 1 0
Partial products First stage
Bit position
6 5 3 2 1 0 6 5 3 2 1 0
Second stage Final adder
FA HA
(a) (b)
(c) (d)
WSubstantial Hardware Savings
WHigher Speeds
WPropagation delay O(log
3/2
N)
Wrregular; inefficient for layout
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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a||a.e a||a.e--%ree Hu|t|p||er %ree Hu|t|p||er
Partial products
First stage
Second stage
Final adder
FA FA FA
HA HA
FA

3
y
3
z
7
z
6
z
5
z

z
3
z
2
z
1
z
0

3
y
2

2
y
3

1
y
1

3
y
0

2
y
0

0
y
1

0
y
2

2
y
2

1
y
3

1
y
2

3
y
1

0
y
3

1
y
0

0
y
0

2
y
1
HA
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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a||a.e a||a.e--%ree Hu|t|p||er %ree Hu|t|p||er
F
F
F
F
y
0
y
1
y
2
y
3
y
4
y
5
8
6
|- 1
6
|- 1
6
|- 1
6
|
6
|
6
|
F
y
0
y
1
y
2
F
y
3
y
4
y
5
F
F
6
6 8
6
|- 1
6
|- 1
6
|- 1
6
|
6
|
6
|
W 3 to 2 compression to 2 and higher order compression proposed
W Today's high performance multipliers do ust that!
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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a||a.e a||a.e--%ree Hu|t|p||er %ree Hu|t|p||er
Partial products
First stage
Second stage
Final adder
FA FA FA
HA HA
FA

3
y
3
z
7
z
6
z
5
z

z
3
z
2
z
1
z
0

3
y
2

2
y
3

1
y
1

3
y
0

2
y
0

0
y
1

0
y
2

2
y
2

1
y
3

1
y
2

3
y
1

0
y
3

1
y
0

0
y
0

2
y
1
HA
WFinal adder choice critical; depends on structure of accumulator array
WCarry look ahead might be good if data arrives simultaneously
WPlace pipeline stage before final addition
Wn non-pipelined, other adders similar performance w/ less hardware
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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Hu|t|p||ers Hu|t|p||ers --8ummary 8ummary
pt|m|zat|on Coa|s 0|ffer ent Vs |nar y dder
n.e ga|n: |dent|fy 6r|t|.a| !ath
ther poss|b|e te.hn|ques
- 0ata en.od|ng (ooth}
- !|pe||n|ng
F|R8% CL|H!8E % 8Y8%EH LEVEL !%|H|Z%|N
- Logar|thm|. ver sus L|near (a||a.e %ree Hu|t}
W 5 5 multiplier achieved propagation delay of . ns
W Combined Booth encoding and Wallace tree using -2 compression
W With pass transistors; mixed carry-select and carry look ahead topology
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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8h|fters 8h|fters
Needs extensive hardware support
Used for floating point units; scalers and multiplication by constants
Programmable shifter more complex
an intricate multiplexer circuitry
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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%he |nary 8h|fter %he |nary 8h|fter

i-

i-
#ight Left nop
it-Slice i
...
W Too slow for large shift values
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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%he arre| 8h|fter %he arre| 8h|fter
Sh3 Sh2 Sh Sh0
Sh3
Sh2
Sh

0
: Control Wire
: Data Wire
W rows = data word length
WControl wire routed diagonally
WSignal goes through only one
transmission gate (theoretically
delay is constant for shift value
and shifter size)
WReality delay depends on
shift widths due to parasitic
capacitance
WLayout and area dominated by
wiring and not active elements
WNeed decoder to interpret shift
data to route signal to
appropriate wire
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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4x4 barre| sh|fter 4x4 barre| sh|fter
uffer
Sh3 Sh2 Sh Sh0

0
WIdth
barrc!
~ 2 p
m
M
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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Logar|thm|. 8h|fter Logar|thm|. 8h|fter
Sh Sh Sh2 Sh2 Sh4 Sh4

3
WTotal shift decomposed into
powers of two
Wax shift width of has log
2

stages
Wi
th
stage shifts 2
i
or passes data
unchanged
WSpeed depends on shift length
WSeries connection of pass
transistor slows shifter down for
larger shift values (need
intermediate buffers)
WAppropriate for larger shifts (in
terms of area and speed)
WStructure is regular Can be
parameterised / auto- generated
Vu|l|p||ers ard 3r|llers IEP on Synthesis of Digital Design 2007
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0
Out3
Out2
Out
Out0
0 0--7 b|t Logar|thm|. 8h|fter 7 b|t Logar|thm|. 8h|fter