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Objective
PC
Components - USB
PC
USB
EP 0 EP1 IN
EP1 OUT
Control Endpoint
EP 2 EP 4
Full & High Speed: Up to 30 endpoints configurable as either IN or OUT Low Speed: 2 additional endpoints
EP 6
EP 2 EP 4
EP 6
EP 8
EP 8
Components - USB
PC
USB
Components - USB
PC
USB
Isochronous Mode
Components - USB
PC
USB
Components - USB
PC Start
Endpoint Interrupts
USB
Return
Yes
Components - USB
PC
USB
Components - USB
PC
48 MHz
Bus Powered
PB0-PB7 PD0-PD7
USB
CY7C68013A
EP2 Half Full (>=512 bytes) EP6 Half Full (>=512 bytes) SLRD SLWR SLOE
USB
Components - DSK
PC
PB0-PB7 PD0-PD7 EP2 Buffer EP6 Buffer DSP Routine DSP Routine EXT5 Triggers EDMA Transfer of 512 bytes from the FIFO to EP2 buffer. On completion, the interrupt is cleared and the EDMA channel is ready for the next transfer request. Tx Ping & Tx Pong buffer data are sent to the codec continuously.
USB
ARE AWE
AOE
CE
Out
AIC23 Codec
EP2 Half Full (>=512 bytes) EP6 Half Full (>=512 bytes)
EXT5 EXT4
Rx Ping Rx Pong
In
12
Components - DSK
PC
PB0-PB7 PD0-PD7 EP2 Buffer EP6 Buffer DSP Routine DSP Routine On completion of an Rx ping or Rx pong, the data from the Rx buffers are optionally transferred into the Tx buffers and the DSP routine is called that transfers the data into the EP6 buffer. An EDMA request is then triggered to transfer the EP6 buffer to the FIFO over the EMIF.
USB
ARE AWE
Trigger EDMA
AOE
CE
Out
AIC23 Codec
EP2 Half Full (>=512 bytes) EP6 Half Full (>=512 bytes)
EXT5 EXT4
Transfer Complete Interrupt
Rx Ping Rx Pong
In
13
Reference Cypress CY7C68013A Datasheet EZ-USB Technical Reference Manual USB Complete Jan Axelson