A COMPARATIVE STUDY OF SOI MOSFET STRUCTURE FOR LOW POWER APPLICATION

PREPARED BY: KHAIRUL AFFENDI BIN ROSLI (P60850) RAJA MOHD NOORHAFIZI BIN RAJA DAUD (P60849) LECTURER: AP DR. MAMUN IBNE REAZ

CONTENTS
Introduction Target Application Review-Comparative studies Discussion Latest technology Conclusion Reference

INTRODUCTION
What is MOSFET?
 Metal Oxide Semiconductor Field Effect Transistor  Was first patented by Julius Edgar Lilienfeld in 1925  Source(supplies carrier) & Drain (receives carrier)  As a switching or amplifying electronic signal

MOSFET STRUCTURE

What is SOI Technology

SOI-Silicon on insulator, refers to placing a thin layer of silicon on top

of an insulator such as SiO2

The basic concept of SOI is to produce a reduction of the parasitic

capacitance in order to increase the switching speed

Supply voltage can be lowered to cut the power consumption while

adequate speed is provided.

BULK CMOS

SOI CMOS

SOI Structure

Comparison between the BULK CMOS and SOI CMOS in term of leakage current path

TYPES OF SOI MOSFET

Partially Depleted SOI MOSFET Fully Depleted SOI MOSFET  Undepleted neutral region at the  Entire Region of SOI layer is fully bottom of the SOI Layer. depleted.  Maximum depletion width is  Maximum depletion width is greater lesser than the thickness of SOI than the thickness of the SOI [3] when the channel is inverted[3]  Insulating BOX layer may also  Insulating BOX layer is typically ultrathin,5nm to 10nm. 100nm to 200nm

PDSOI MOSFET vs FDSOI MOSFET

Types of SOI MOSFET Partially Depleted SOI MOSFET Advantages Challenging

 Easy to manufacture  Physical limits to scalability  Can leverage floating body for are approaching for high performance gain or memory performance applications.  Leakage and power  New metrology needed for consumption are drastically detect defection in very reduced thin layers.  No floating body effects,  Very thin body can be easier to control short channel challenging to manufacture effects. and implement performance boosters.

Fully Depleted SOI MOSFET

TARGET APPLICATIONS PDSOI

 High performance microprocessor  Analog, RF, automotive  Power  Military

FDSOI
 High performance microprocessor  Low-power electronics  Ultra-Low power

REVIEW-COMPARATIVE STUDY
Low power applications such as DTMOS, RF technology

i) DTMOS by (Assaderaghi et al.-1997) Dynamic threshold voltage MOSFET By tying the gate and the body of an SOI MOSFET together.
Cross section of an SOI NMOSFET with body and gate tied together.

In theory, ideal subthreshold swing and higher carrier mobility

than the standard MOSFET. A single MOSFET can have a higher threshold voltage when the voltage at gate to source equal to zero hence produced a reduction in leakage current and higher speed operation

DTMOS (contd.) (Lee et al.-1998) - proposed new design auxiliary MOSFET gate and drain are shorted to main transistors gate and source is connected to the channel body of the main transistor

DTMOS (contd.) Resulted-low threshold voltage, high operation voltage and high drain current as compared to conventional MOSFET and previous DTMOS designs. Improved subthreshold voltage by 11% and increased drain current capability by 46% and decreased the leakage current.
Items Vth Swing ID Conventional 0.675V 86.8 mV/dec 38.2 A DTMOS 0.47V 80 mV/dec 102.3 A Proposed 0.608V 68 mV/dec 66.1 A

 (Han et al.- 2006) research on body effect of the

DTMOS. The back gate (bulk substrate) was utilized to offer the dynamic threshold voltage operation that exhibits high Vt at Vg=0V to and low Vt at Vg=Vdd=0.6V to achieve low power and high performance. In order to maximize inactive opportunity of large body factors, sufficiently large fin width structures are highly demanded.

 ii) RF Performance for Low Power Low Voltage - People nowadays getting busier - so, high demand for

multitasking electronics devices-iPad2 and Galaxy Tab. - 2 important crucial things: Sizeability of those devices (need to be smaller size) Higher output power with smaller power consumption. i.e WiFi application. - SOI MOSFET have the answer.

 Deen et al.-research on RF function in low power low voltage

application - achieved better performance compared to previous design by Wong et al , Tarim et al and Seng et al.
Researchers Supply voltage Output bandwidth (3 dB) Power consumption Seng et al. + - 1V 4.3 MHz 0.13 mW Tarim et al 99 MHz 1.5 mW Wong et al 1.5V 2.4 GHz 3.7mW Proposed (Deen et al.) 1.2V 3GHz 1.32 mW

Applying an input to the body terminal of the transistors. The

primary advantage of this circuit topology is low-voltage and low-power operation. The measured results show operation at 1.2V with a power consumption of 1.32mW, while maintaining good performance.

 Thermal conductivity of the SOI MOSFET- crucial thing. The buried oxide (BOX)-got a poor thermal conductivity

caused a huge temperature rise (up to 80 degree C). Resulted- the device characteristic will shift and caused malfunction. Emam et al - research on 130nm PDSOI MOSFET on a high density substrate with two different architectures which are Floating-Body and Body-Tied type. Experiment resulted that the negative effect of rise temperature in RF behavior can be turned into positive effect . A tiny cutoff frequency - sufficient for specific applications while maintaining the minimum power consumption and maximized the battery lifetime. As example, a typical WiFi application consumed of VDS = VGS = 1.2 V and power consumption at 645 mW/mm. The proposed design resulted a VDSbias, VGS, power consumption equal to 0.6 V, 0.2 V and 0.23mW/mm respectively.

DISCUSSION
By utilizing the floating body effect, the performance gain

can be increased and also memory application. For DTMOS, connection tie on both the gate and the body together, a SOI MOSFET can have a higher threshold voltage.  PDSOI face main drawback(physical limitation and heat behavior) FDSOI can reduce the leaking current and improved power consumption.

DISCUSSION(CONTD)
Latest Technology of SOI MOSFET
AMD announced on 24th November 2011 that they have

built a next generation CPU core on 32nm SOI Leakage power reduced by 95% when both core were ideal hence improved the low voltage margin and read timing. 213 million transistors/modules, 11 metal layers with 0.8 1.3V operation.

AMDs Bulldozer CPU Core

CONCLUSION
SOI technology is very flexible in term of design and

various applications especially in low power low voltage characteristic. The most appropriate candidate for low power application is Fully Depleted SOI MOSFET due to great advantages in term leakage and power consumption are drastically reduced ,no floating body effect and easier to control short channel effects. However, PDSOI structure is easy to manufacture yet a lot of researches still conducted to optimize it function.

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THANK YOU FOR YOUR TIME

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