BJT Inverter (Transistor Switch)

Transistors (BJT) are widely used in digital logic circuits and switching applications. The fundamental transistor circuit used in switching applications is called an inverter. The transistor is in CE configuration and no bias voltage is connected to the base through a resistor, but a resistor RB is connected in series with the base and then directly to a pulse-type wave that serves as the inverters input. In the circuit, VCC and the high level of input are both +5V. The output is the voltage between collector and emitter (VCE = vout) .
S. Kal, IIT-Kharagpur

When the input is high ( + 5V), the B-E jn. jn. is forward biased and current flows through RB in to the base. The values of base. RB and RC are chosen such that the IB is enough to saturate the transistor. Note transistor. that the value of VCE in saturation is nearly 0 ( typically VCE(sat) } 0.2 V ). When the transistor is saturated, it is said to be ON and the high input to the inverter (+ 5 V) results in a low output ( } 0 V). V). When the input to the transistor is low, ie, 0 V, the B-E jn. is not forward biased, so jn. no base current, and hence no collector current flows. There is no voltage drop flows. across RC and it follows that VCE = VCC. The transistor is in cut off region and is said to be OFF. A low input to the inverter OFF. results in a high output and thus the circuit is called an Inverter. Inverter.
S. Kal, IIT-Kharagpur
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Inverter Design


In designing inverter, it is assumed that IC(sat) = VCC/RC and VCE(sat) = 0 Since the transistor is cut off when the input is low, regardless of the values of RB and RC, the equations to be used are those that apply when input is high.

VCC = VCE + IC RC IC = IC(sat) = VCC / RC IB = IC(sat) / F = VCC / FRC

and IB = ( VH VBE) / RB where VH is high level of the input voltage.


To design a transistor inverter we must have criteria for specifying the values of RB and RC. Typically, one of the values is chosen, and the value of the other is derived. The relationship of RB and RC are
S. Kal, IIT-Kharagpur
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Inverter Design
RB = (VH VBE)/IB = ( VH VBE) F RC / VCC RC = VCC / FIB = VCC RB / F (VH VBE) Since these equations are valid for a specific values of F, they are not entirely practical. F varies over a wide range. If the actual value of F is smaller than the one used in the design equations, the transistor will not saturate. So F in design eqn. must be smallest possible value that might occur in a given application. So the RB and RC are expressed in the form of inequalities, RB e (VH VBE)/IB = ( VH VBE) F RC / VCC RC u VCC / FIB = VCC RB / F (VH VBE)
S. Kal, IIT-Kharagpur

Diode Logic (OR gate)



A = low, B = low, both diodes D1 and D2 are non-conducting, so output, y = 0 A = high, B = low, D1 conducts, D2 is non-conducting, so output, y = (5 0.7) V = 4.3 V ( high) A = low, B = high, D2 conducts, D1 is non-conducting. Therefore, output, y = (5 0.7) V = 4.3 V ( high) A = high, B = high, both diodes D1 and D2 are conducting. Therefore, output y = (5 0.7) V = 4.3 V ( high)
S. Kal, IIT-Kharagpur

Diode Logic (AND gate)

If any of the input is 0, that particular diode is forward biased and the output voltage (y) will be diode drop, i.e. y = 0.7 V (logic 0) When A = high, B = high, i.e. both inputs are at 5 V, both the diodes (D1, D2) are not conducting because the voltage across the diodes is 0. Since no current flows through RL, the output is pulled on to the supply voltage (VCC = 5 V). Therefore, y = high.
S. Kal, IIT-Kharagpur

Resister Transistor Logic (RTL) NOR gate



If any of the inputs (A, B) becomes high (= 5 V), that particular transistor goes into saturation and the output is almost 0 V (= VCE (sat)). If both the inputs (A, B) are at logic low level (logic 0 = 0 V), then switches are cut off and no current flows through RL. So the output y = + 5 V (logic high).

S. Kal, IIT-Kharagpur
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Diode Transistor Logic (DTL) NAND gate



If any input A or B or both A & B are low, Diode D1 / D2 conducts and point X will be at 0.7 volts @ T1 p Off & y = High If A and B are high (5V), diodes D1, D2 will not conduct, but D3, D4 conducts and so T1 p on (saturation) as the voltage at point X is more than 2.1 V @ y = VCE(SAT) and output of T1 = Low Thus the circuit is a NAND gate
S. Kal, IIT-Kharagpur
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Transistor Transistor Logic (TTL) Inverter



TTL introduced by Texas Instruments in 1964 is a widely used logic family of digital circuits. In TTL, base of T2 is connected to collector of T1 whose emitter is used as input terminal. The emitter of T2 is grounded and its base voltage and hence the collector of T1 will not rise above 0.75 V[ VBE(sat)]. If vin is high(~ 5V), the B-E Jn of T1 is reverse bised and its C-B jn is forward biased. Thus, the transistor T1 is in inverse mode of operation.Then IC1 drives T2 and it will be ON. 1. vin= high, T1 is in inverse mode, T2 = ON, vout = VCE(sat) = low 2. vin = low, T1 is in normal mode, T2 = cut off, vout = Vcc = high
S. Kal, IIT-Kharagpur
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TTL NAND gate

If any of the inputs is at logic level 0, T1, is in normal mode of operation, T3 p cut off. output is at level 1 If all the inputs are at logic 1, T3 is in saturation and the output is at logic 0. Emitter of T1 } 5V, Base of T1 < 5V, B-E jn p R.B. Base of T3 } 0.75 (maxm). C-B jn of T1 p F.B. T1 works in inverse mode IC1 } IB2 T3 drives into saturation, Y = VCE(sat) of T3
S. Kal, IIT-Kharagpur

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TTL NAND Gate with Totem-Pole output

Integrated circuit TTL is fabricated with a totem-pole pair output circuit to allow high speed swit-ching and a large fan out. In an IC TTL NAND gate, T1 and T2 are integrated into a single transistor with two emitters. If necessary, more emitters can be fabricated on the same base and multiple input TTL gates may be obtained. Each emitter acts like a diode; therefore, T1 with 4-k; resistor (RB) acts like two-input AND gate. The rest of the circuit inverts the signal and the overall circuit acts like a two-input NAND gate
S. Kal, IIT-Kharagpur
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TTL NAND Gate with Totem-Pole output

The input voltages A and B are either low (grounded) or high (5V). If A or B is low, T1 saturates. This reduces the base voltage of T2 to almost zero. Therefore, T2 cuts off, forcing T4 to cut off. Under these conditions, T3 acts like an emitter follower and couples a high voltage to the output. On the other hand, when both A and B are high, the collectorbase junction of T1 becomes forward biased and its collector diode goes into forward condition; this forces T2 and T4 into saturation, producing a low output. Incidentally, without diode D1 in the circuit, T3 would conduct slightly when the output is low. The voltage drop by the diode keeps base-emitter diode of T3, reversebiased. So only T4 conducts when the output is low. Thus, the circuit behaves as a NAND gate.

S. Kal, IIT-Kharagpur

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TTL NAND Gate with Totem-Pole output

The output transistors (T3 and T4) form a totem-pole connection. Either transistor T3 or transistor T4 is on. The output is high when T3 is on and it acts like an emitter follower. The output is low when T4 is on and no current flows through RC. This is important because it keeps the circuit power dissipation down.


The advantage of a totem-pole connection is its low-output impedance, which reduces the switching time. The advantage of this arrangement occurs in the output high state. Here T3 is acting as emitter follower with its associated low output impedance (typically, 10;). This low-output impedance provides a short time constant (RC) for charging up any capacitive load (C) on the output. This action is known as active pull-up and provides very fast rise-time waveforms at TTL outputs.


A standard TTL gate has a power dissipation of about 10 mW and a propagation delay time of nearly 10 ns.

S. Kal, IIT-Kharagpur
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N-MOS Inverter and Logic Gates

1. MOSFETs can act both as amplifier / driver and as a load resistor, eliminating the need for ordinary load resistors, which consume large area in silicon ICs. MOSFETs take up very little area compared to Si-BJTs so that more circuits can be formed on a wafer. Circuits using MOSFETs have higher yield. Enhancement type MOSFETs are preferred over depletion type because the former can be switched ON or OFF with the supply and also a single polarity supply is sufficient.
S. Kal, IIT-Kharagpur
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2.

3. 4.

N-MOS Inverter
are used in this circuit. Instead of passive resistive load, M1 is used as an active load while M2 is used as a switching/driver transistor. M1 is always in ON state, as it is permanently connected to +5 V and essentially RON will be the load resistance. In response to the input gate-source voltage (Vin), M2 will switch from ON to OFF state. M1 is designed to have a narrower channel than M2 so that ON state resistance (RON) of M1 is greater than that of M2. Typically, RON of M1 and M2 are 100 k; and 1 k;, respectively. ROFF of M2 is around 1010 ;. We many analyze this circuit considering each MOSFET channel as a resistance so that output voltage is taken from a voltage divider formed by two resistances. With Vin = 0 V, M2 is off, with a very large channel resistance of 1010 ;. Since M1 has RON } 100 k;, the voltage divider output will be essentially 5 V. On other hand, with Vin = 5 V, M2 is on, with RON } 1 k;. The voltage divider output is now nearly 0.05 V. Thus, the circuit functions as an inverter since a low input produces a high output, and vice versa.
S. Kal, IIT-Kharagpur
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In a basic N-MOS inverter circuit, two N-channel MOSFETs (M1 and M2)

(a) MOS NAND gate

(b) MOS NOR gate

S. Kal, IIT-Kharagpur

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CMOS Inverter


CMOS inverter utilizes two matched enhancement type MOSFETs: one M2, with n-channel and the other M1, with a pchannel. The body of each device is connected to its source and thus no body effect arises. In a CMOS switch, n-MOS and p-MOS are joined at their drains and the series combination is connected across the supply voltage (VSS). +Vss is connected with source p-MOS and Vss is connected to the source of n-MOS and grounded. The output is taken at common drain and the input is applied in common to both gates. Both p-MOS and n-MOS transistors operate in E-mode. Vi swings from ground voltage (~0V) to +VSS.
S. Kal, IIT-Kharagpur

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CMOS Inverter


When Vi } ground ~ 0 V, M2 will be OFF, because VGS(QN){ ~ 0} < VT and M1 will be ON, because, VGS(M1) { ~ VSS} > VT . @V0 = VSS. When Vi } VSS, (logic high) M2 will be ON, because VGS(QN) {~VSS} >VT and M1 will be OFF, because, VGS(M1) { ~ 0} < VT .@V0 = 0. High gm of M2 will have small drop w.r.t. ground. Gate of M1 is at zero volts with respect to source
S. Kal, IIT-Kharagpur

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Advantages of CMOS Inverter

1. 2. 3. 4.

In CMOS, V0 = full supply voltage, when Vi = 0. When Vi } VSS, V0 approaches a very low value (}10 mV) Transition between two levels ( 0 and VSS) much sharp When switch is at one or the other limit of its range, its power dissipation is normally zero. Because in High or Low case one or the other FET is cut off. The current supplied by the supply voltage is nominally zero ( except leakage current } 10 nA). Impedance looking into the gate of FET is }109 ;, so in the quiescent condition, there is no power dissipation.
S. Kal, IIT-Kharagpur

5.

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CMOS NAND gate

CMOS NOR gate

S. Kal, IIT-Kharagpur
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