Transmission Synchronization

By shrihari chintala

SDH basics
>The SDH Frame transports a PDH payload within VCs aligned in TUs and AUs with pointers VC12 carrying 2 Mbit/s tributary are aligned in TU12 via a 1 byte pointer TU12 are multiplexed into TUG 2 & 3 then mapped into VC4 VC4 are aligned in AU4 via a 3 byte pointer

Why synchronizing SDH networks?

>The G.707 frame has internal mechanisms, called pointer processors, that allow SDH to work in a non synchronized environment. Pointers allow desync between 2 equipments without significant effect on the PDH payload (although some problems appeared at the beginning of SDH (35/1 effect) deployment in the fields, which have been solved 10 years ago) Within an SDH network, there is no problem in the SDH frame in case of any case of desynchronization, even if all NEs are desynchronized.

Why synchronizing SDH networks?

>But, Accumulation of pointers due to multiple desynchronization may generate excessive jitter and wander on PDH payload May generate LOF on PDH payload due to buffer overflow or underflow

How to synchronize SDH networks

It must be possible to provide synchronization to SDH and to transport this synchronization between the SDH Nes SDH NEs must be able to receive timing from reference Sources via dedicated external ports

How to synchronize SDH networks

Transport of timing by the STM-N signals Noise is accumulated along the chain of clocks. This is a major issue for transporting timing via STM-N signals Solutions masterslave sync architecture Hierarchical clocks clock for the SDH NEs SSM in G.707

Clock types
> 3 types of clock G.811 Primary Reference Clock (PRC) G.812 Synchronization Supply Unit (SSU) G.813 SDH Equipment Clock (SEC)

SSM and ring architecture

SSM and ring architecture

> SSM definition A 4 bit code located in S1 byte of STM-N frame Indicates the Quality Level of the source of synchronization >SSM application Prevent timing loops In linear chains and rings In any combination of them In meshed networks with some restrictions Helps in desynchronization detection

Synchronization Loops

FIBCOM MUX
Configuring the Synchronization Sources

Configuring the Synchronization Sources

The Fibcom 6325 node supports the SDH synchronization management with full protection of the synchronization network. It is possible to synchronize a Fibcom 6325 node on the following sources: An incoming SDH signal An incoming 2 Mbit/s signal 2,048 kHz or 2 Mbit/s clock signals Fibcom 6325 node furthermore delivers an external synchronization clock: 2,048 kHz or 2 Mbit/s clock signals

Configuring the Traffic Port Inputs as Synchronization Sources

Select Transport Synchronization... in the pop-up menu of the NE icon. The Synchronization window appears

Assign Sources....

Configuring the Input Quality of a Synchronization Source

Value Description

QL-PRC QL-SSU-A QL-SEC QL-DNU QL-NSUPP

The synchronization source transports a synchronization quality generated by a Primary Reference Clock. The synchronization source transports a synchronization quality generated by a Synchronization Supply Unit with "A" quality. The synchronization source transports a synchronization quality generated by an SDH Equipment Clock. Do Not Use. This signal should not be used for synchronization. This quality level is automatically assigned to a synchronization source which is not supporting SSM. The quality should normally be overwritten with a provisioned value. An invalid SSM code has been detected. This applies for STM-<n> traffic port inputs and 2 Mbit/s station clock inputs with SSM. A Server Signal Fail (SSF) condition is present. The synchronization signal is lost.

QL-INV QL-FAILED

Configure Selector A

Operate...

Configuring the Station Clock Outputs

Configuring the Traffic Port Outputs

Synchronization

ECI MUX
Configuring the Synchronization Sources

Modify-Ref A-select one E1 from first 4 E1 Modify-Ref B-select one E1 from first 4 E1

Select Quality PRC

TEJAS MUX
Configuring the Synchronization Sources

Configuration Management Synchronization Status

To View and edit the Synchronization Status
Click Configuration in the navigation menu. The list of features that can be provisioned is displayed in the sub menu area

Click Synchronization. Click Synchronization Status. Synchronization State page is displayed

Enter appropriate values against relevant fields

Click Submit. A success message is displayed upon confirmation

Configuration Management Timing Reference

To View Clock Select
Click Configuration in the navigation menu. The list of features that can be provisioned is displayed in the sub menu area

Click Synchronization. Click View nominated timing reference

View nominated timing references page is displayed

Configuration Management Timing Reference

To Nominate a Clock
Click Configuration in the navigation menu. The list of features that can be provisioned is displayed in the sub menu area

Click Synchronization. Click Nominate timing reference. Nominate timing references page is displayed

Select the appropriate values against fields. Click Submit

Success message is displayed

Configuration Management Timing Reference

To Delete a Clock
Click Configuration in the navigation menu. The list of features that can be provisioned is displayed in the sub menu area

Click Synchronization. Click View nominated timing reference. View nominated timing references page is displayed

Select the clock reference that is to be deleted against the delete field. Click Submit

A confirmation page is displayed. Success message is displayed upon confirmation

HUAWEI M/W link

Configuring the Synchronization Sources

PROCEDURE WHEN SOURCE IS FIBER

To Check clock source

Starting SSM Protocol

To check the Clock Quality

To check SSM output control

PROCEDURE WHEN SOURCE IS MW

To check the SSM protocol

To check the Clock Quality

To check SSM output control

Motorola BSC & BTS phase lock

Clock Extraction

Procedure for Phase locking of BSC

 Check the status of GCLK of BSC

State 0 gclk * *
IF GCLK in status of failed phase lock Check the element value of BSC

disp_element phase_lock_gclk <location>

Where: <location> is: 0 or bsc, for a BSC 0 for an XCDR If phase_lock=0 The GCLK is in set frequency mode If phase_lock=1 The GCLK is in phase lock mode

Selecting the MMS for for providing clock

 First check link diagram and select the MMS to be used for providing clock  Ensure that MMS is in cage 0  Ensure that MMS_Priority should be 255  Shortest path from MSC

Priority assigning to MMS

 If priority of MMS selected is not 255 Modify the value of priority modify_value <location> mms_priority 255 mms <mms id>  Also ensure that other MMS should have low priority,  If not change the priority less than 255 modify_value <location> mms_priority 254 mms <mms id> Where: <location> is 0 to 40, or bsc

Attempt to lock
 For attempting to phase_lock value to 1,  chg_element phase_lock_gclk 1 <location> Where: <location> is 0 to 40, or bsc.  Ensure that MMS providing clock as per planned  Check the status of GCLK state <location> gclk * *

Sustaining Phase_lock
 Avoid the synchronization loop  Modify the changes in transmission and reattempt by

reattempt_pl bsc 0
 Phase_lock_duration: The phase_lock_duration parameter extends the minimum length of time a GCLK must hold synchronization with an MMS before the GCLK is considered synchronized The phase_lock_duration parameter is set as an integer within the range 0 to 3600 seconds.  There is no default or recommended value

 modify_value <location> phase_lock_duration <new_value> mms <dev_fun_id1><dev_fun_id2><dev_fun_id3>

Sustaining Phase_lock
 phase_lock_retry The phase_lock_retry parameter speci es the time in minutes during which phase locking is automatically retried after failure

disp_element phase_lock_retry <location> chg_element phase_lock_retry <value> <location>

Value type Valid range Integer (minutes) 0 to 255 0 Immediate phase_lock_retry 1 to 254 Time period for retrying phase locking 255 No phase_lock_retry 255

Default value

Thank You