Digital System

Xilinx FPGA Design Flow

Ping-Liang Lai (

Outline of FPGA Design Flow

Project Navigator
  

I:

Schematic
(Project) (Schematic) (Functional Simulation)

Testbench :

Modelsim Simulator

Implementation Constraints File Implementation Design (Timing Simulation) Configuration

Modelsim Simulator

II:

Verilog

Project Navigator

(1/2)

Multi-document Interface Source

Process Source

Transcript

Project Navigator
Source  Sources Tab

(2/2)

(Project) Design View Snapshot Project

FPGA/CPLD

Snapshot Tab

Snapshot Library

Project

Library Tab

Processes Source


Transcript  Console, Error, Warning, Tcl Console, and Find in Files.

Outline of FPGA Design Flow

Project Navigator
  

I:

Schematic
(Project) (Schematic) (Functional Simulation)

Testbench :

Modelsim Simulator

Implementation Constraints File Implementation Design (Timing Simulation) Configuration

Modelsim Simulator

II:

Verilog

(1/8)
Step 1: File

New Project

(2/8)

FPGA

: Spartan 3 XC3S200-FT256

(3/8)
Step 2:

Source

Schematic

(4/8)
New Source Summary

(5/8)
We only need one Source, so Next.

(6/8)
We dont need and have any Existing Sources, so Next.

(7/8)
New Project Summary

(8/8)

1. Source Device

, 2.

Outline of FPGA Design Flow

Project Navigator
  

I:

Schematic
(Project) (Schematic) (Functional Simulation)

Testbench :

Modelsim Simulator

Implementation Constraints File Implementation Design (Timing Simulation) Configuration

Modelsim Simulator

II:

Verilog

Schematic
Schematic

(1/5)

Add I/O Maker

Add wire

Add Net Name Add Symbol

Schematic
Step 3: Add

(2/5)

Symbol and Wire.

Schematic
Step 4: Add

(3/5)

IO Maker.

Schematic
Step 5: Add

(4/5)

Net name.

Schematic
Step 6: Tool

(5/5)

Check schematic, and check no error and Save.

Outline of FPGA Design Flow

Project Navigator
  

I:

Schematic
(Project) (Schematic) (Functional Simulation)

Testbench :

Modelsim Simulator

Implementation Constraints File Implementation Design (Timing Simulation) Configuration

Modelsim Simulator

II:

Verilog

(1/12)
Step 7: Source for Behavioral Simulation

fa (fa.sch) add new source

fa_tbw

(2/12)
We only have one source, so Next.

(3/3)
New Source Summary

(4/12)

(5/12)
Step 8:

input

n inputs

2n input combinations.

(6/12)
Step 9: Modelsim Simulator

Simulate Behavioral Model (Double click

mouse left key 2 times).

(7/12)

Modelsim Simulator

You can see Error Loading .

(8/12)
Step 10: Select work

Compiler AND2, OR3, and XOR2. (file path: C://Xilinx/9.2i/ISE/verilog/src/unisims)

(9/12)
Step 11: In fa_tbw, Right click

Simulate

(10/12)
Step 12: Right Click fa_tbw to select Add

To Wave

All items in

region.

(11/12)
Behavioral Waveform Window

(12/12)
Step 14: Run all, and Step 15: Zoom fit.

Outline of FPGA Design Flow

Project Navigator
  

I:

Schematic
(Project) (Schematic) (Functional Simulation)

Testbench :

Modelsim Simulator

Implementation Constraints File Implementation Design (Timing Simulation) Configuration

Modelsim Simulator

II:

Verilog

Implementation Constraints File

Step16: Sources for Synthesis/Implementation Step 17:

(1/8)

fa.sch Project

New Source

Implementation Constraints File

(2/8)

Implementation Constraints File

Step 18:

(3/8)

fa.ucf User Constraints

Assign Package Pins.

Implementation Constraints File

Xilinx PACE

(4/8)

Implementation Constraints File

Step 19:

(5/8)
I/O Pins

Package View

Design Browser

Implementation Constraints File

Step 20:


(6/8)
Datasheet

Spartan-3 FPGA XC3S200-FT256

Slide Switches

LEDs

Implementation Constraints File

(7/8)

File Save

Implementation Constraints File

(8/8)

Edit Constraints (Text)

Outline of FPGA Design Flow

Project Navigator
  

I:

Schematic
(Project) (Schematic) (Functional Simulation)

Testbench :

Modelsim Simulator

Implementation Constraints File Implementation Design (Timing Simulation) Configuration

Modelsim Simulator

II:

Verilog

Implement Design (1/6)

Step 21: Implement Design

Implement Design (2/6)

Implement Design (3/6)

Place & Route LUT

View/Edit Routed Design (FPGA Editor)

Implement Design (4/6)

FPGA

(Design Summary

Summary)

Implement Design (5/6)

Pinoout Report (Design Summary

Pinout Report)

Implement Design (6/6)

: Generate Post-Place & Route Static Timing Post-Place & Route Static Timing.

Analyze

Outline of FPGA Design Flow

Project Navigator
  

I:

Schematic
(Project) (Schematic) (Functional Simulation)

Testbench :

Modelsim Simulator

Implementation Constraints File Implementation Design (Timing Simulation) Configuration

Modelsim Simulator

II:

Verilog

(Timing Simulation)

Functional Simulation

Outline of FPGA Design Flow

Project Navigator
  

I:

Schematic
(Project) (Schematic) (Functional Simulation)

Testbench :

Modelsim Simulator

Implementation Constraints File Implementation Design (Timing Simulation) Configuration

Modelsim Simulator

II:

Verilog

Configuration
Step 22: Generate Programming File

(1/2)

Configuration

(2/2)

Configure Device (iMPACT) Step 22: iMPACT Configure devices using Boundary-Scan (JTAG) Automatically

Outline of FPGA Design Flow

Project Navigator
  

I:

Schematic
(Project) (Schematic) (Functional Simulation)

Testbench :

Modelsim Simulator

Implementation Constraints File Implementation Design (Timing Simulation) Configuration

Modelsim Simulator

II:

Verilog

II:

Verilog

From Step 2 to choose a Verilog Module, and repeat Step3 ~ Step 22. Design example: 4-bit Ripple Carry Counter

reset 1 1 0 0

ck * *

qn 1 0 0 1

qn+1 0 0 1 0