High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics

Hardware implementation of NikhiIam Sutra

INTRODUCTION
Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 sutras(formulae). It is used for calculating complicated arithmetical operations,and to a extent ,executing them mentally. On account of those formulae, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay in comparison with DA based architecture and parallel adder based implementation.

 The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectra using standard 90nm CMOS technology. The propagation delay of the resulting (16,16)X(16,16) complex multiplier is only 4ns and consume 6.5mW power as compared to the normal multiplier which takes 11 ns. We achieve almost 25% improvement in speed from earlier reported complex multipliers

VEDIC MULTIPLICATION The proposed Vedic multiplier is based on the Vedic multiplication formulae NIKHILAM SUTRA. These Sutras have been traditionally used for the multiplication of two numbers in the decimal number system. In this work, we apply the same ideas to the binary number system to make the proposed algorithm compatible with the digital hardware. Vedic multiplication based on NIKHILAM SUTRA as discussed below :-

Nikhilam Sutra Nikhilam Sutra literally means all from 9 and last from 10. Although it is applicable to all cases of multiplication it is more efficient when the numbers involved are large. Since it finds out the compliment of the large number from its nearest base to perform the multiplication operation on it, larger is the original number, lesser the complexity of the multiplication. We first illustrate this Sutra by considering the multiplication of two decimal numbers (96 * 93) where the chosen base is 100 which is nearest to and greater than both these two numbers. We should take the power of 10 as base.

Multiplication Using Nikhilam Sutra

 The right hand side (RHS) of the product can be obtained by simply multiplying the numbers of the Column 2 (7*4 = 28). The left hand side (LHS) of the product can be found by cross subtracting the second number of Column 2 from the first number of Column 1 or vice versa, i.e., 96 7 = 89 or 93 - 4 = 89. The final result is obtained by concatenating RHS and LHS (Answer = 8928)

COMPLEX MULTIPLIER USING VEDIC MATHEMATICS

We formulate this mathematics for designing the multipier architecture in transistor level with two goals such as 1) simplicity and modularity multiplications for VLSI implementations and 2)The elimination of carry propagation for rapid additions and subtractions. Complex number multiplication is performed using four real number multiplications and two additions/subtractions. By employing the Vedic mathematics,an N bit complex number multiplication was transformed into four multiplications for real and imaginary terms of the final product. Nikhilam sutra is used for the multiplication purpose, with less number of partial products generation. The multipier is fully parameterized,so any configuration of input and output word-lengths could be elaborated.

HARDWARE IMPLEMENTATION OF EXPONENT DETERMINENT

PIPO(Parallel input Parallel Output) Shifter:

For the non-zero number shifting operation is executed using PIPO shift registers. Each bit is shifted to left ones till 1 is obtained at the MSB. The number of select lines is chosen as per the binary representation of the number(N-1)10 SHIFT pin is assigned in PIPO shifter to check whether the number is to be shifted or not. To initialize the operation, SHIFT pin is initialized to low.

Decrementer:
A decrementer has bee integrated to follow the maximum power of the radix. For an N bit number, the value (N-1)10 is fed to the input of decrementer. The decrementer is decremented based on a control signal which is generated by the searched results. If search bit is 0 then the control signal becomes low then decrementer starts decrementing the input value. If search bit is 1 then the control signal becomes high and the decrementer stops further decrementing and shifter also stops shifting operation. The output of the decrementer shows the integer part(exponent) of the number.

WORKING :
Using exponent determinent, the integer part or exponent of the number can be obtained by the maximunm power of the radix-2. Input X is given to the PIPO shifter. The shifter shifts the input by 1 bit to the left. With the help of select lines, MSB is selected and fed to the decrementer. This acts as the control signal to the decrementer. For an N bit number, the value (N-1)10 is fed to the input of decrementer. If the MSB is 0, control signal becomes low then decrementer starts decrementing the input value. If the MSB is 1 then the control signal becomes high and the decrementer stops further decrementing and shifter also stops shifting operation. Output is obtained from the decrementer, which is the integer part(exponent) of the input X.

The working of the RSU can be explained as per the Block diagram : First the input X that is of N bits is given to the exponent determinant which gives the exponent of X. eg:- X is 17 i.e. 2^4+1 exponent is 4. The exponent is fed to two blocks respectively a) The adder and the shifter combination which calculates the value 2^n. The adder adds a carry to the maximum value of the exponent and the shifter generates 2^n.

b) The shifter block which shifts the exponent to find 2^(n-1). The output of these two blocks is fed to the mean determinant which determines the mean (2^(n-1)+2^n)/2. Next this output is fed to the comparator which compares the output of the mean determinant and the input X and gives a result 0 or 1. if X>A ; Output 1. if X<A ; Output 0. Where A is the output of the mean determinant.

 In the end there is a mux which selects the required radix depending upon the output of the comparator. if Output is 1; radix is 2^n. if Output is 0; radix is 2^(n-1). Using these basic building blocks, the RSU and the exponent determinator, the hardware Implementation of NIKHILAM SUTRA can be Carried out.

Representation
We represent the numbers to be multiplied in the form as mentioned earlier but with base number being powers of 2. The RSU output gives the radix of the number thus represented as k1/2 and the residue is represented by z1/2 where 1/2 indicates either input 1 or 2 respectively.

Equations

Implementation
The block diagram of the implementation using the equation obtained is as shown

The hardware implementation logic

The input is given to the RSU to determine the nearest radix in the powers of 2. The RSU output is given to the exponent determinator to give the exponent of the input number. This value is subtracted from the input using a subtractor that gives the residue of the input. The process is repeated for the other input as well. Both the residues are multiplied using a multiplier to obtain the highlighted portion of the equation.

Note: We also have the value of the exponent.

 The exponents of both inputs are subtracted using a subtractor. The residue of 2nd input is as input to the shifter and the count is given as the output of the subtractor Note: Each time a number is left shifted , the number doubles itself The output of shifter obtained is added/subtracted by the 1st input by the adder/subtractor to obtain the highlighted portion of the equation.

 The output thus obtained is given as input to a shifter with the count being the exponent value of 2nd input. The product thus obtained, is given to an adder/subtractor which adds/subtracts to get the final output given by the highlighted equation.