Computer Architecture - An overview

Unit-1

Basic functional units of a computer

Connections between the processor and the memory

BASIC OPERATIONAL CONCEPTS

Fetching & execution of instructions Instruction address from PC PC to MAR Using control signals MAR -> Memory ->MDR -If instruction MDR -> IR - If data MDR -> register Execute instruction

INTERRUPTS
Interrupt is a request from an I/O device for service by the processor Interrupt service routine Example - ctrl,alt & del

Single-bus structure
Input Output Memory Processor

BUS & BUFFER

A group of lines that serves as a connecting path for several devices "BUS To hold the information during transfers "BUFFER REGISTERS

SYSTEM SOFTWARE ESSENTIAL FUNCTIONS

Receiving and interpreting user commands Entering and editing application programs File management Application program management Controlling I/O units Program Translation Linking & Running

SYSTEM SOFTWARE KEY COMPONENTS

Compiler Text editor Operating system

User program and OS routine sharing of the processor.

PERFORMANCE
"Elapsed Time" - Total time required to execute the program "Processor Time" - Sum of the periods during which the processor is active

The processor cache.

PROCESSOR CLOCK

"clock" - Timing signal that controls the processor circuits "clock cyles" - Regular time intervals defined by clock R=1/P Where

R -> clock rate P -> length of a clock cycle Hertz - cycles per second

BASIC PERFORMANCE EQUATION

T=N*S/R
T -> processor time required to execute a program N -> number of machine language instructions S -> average number of basic steps needed to execute one machine instruction R -> clock rate N * S -> total number of clock cycles needed to execute a program

PIPELINING
Overlapping the execution of successive instructions Example - ADD R1, R2, R3

SUPERSCALAR OPERATION

Implementing multiple instruction in the processor Uses multiple functional units

pipelines

Execution of several instructions in every clock cycle Preservation of logical correctness

HOW TO INCREASE CLOCK RATE

Improving IC technology Reducing the amount of processing done in one basic step

INSTRUCTION SETS

RISC - Reduced Instruction set computer CISC - Complex Instruction set computer

PERFORMANCE MEASUREMENT

Bench Mark Programs Real application programs SPEC

MEMORY OPERATIONS

Two basic operations 1) LOAD (Read or Fetch) 2) STORE (Write)

LOAD OPERATION
Memory contents remain unchanged

LOAD

READ/ADDR ESS DISK

ARITHMETIC UNIT
High speed adders Booth Algorithm High speed multipliers Circuits to perform division operations Representation of floating point numbers in IEEE format Arithmetic operations on floating point numbers

Addition of 1-bit numbers.

0 + 1 + 0 1 + 0 1 1 + 1 1 10

0
0

Carry-out

ADDITION & SUBTRACTION OF SIGNED NUMBERS

Logic specification for a stage of binary addition

Arithmetic operations on floating-point numbers

Add/Subtract Rule Choose the number with the smaller exponent and shift its mantissa right a number of steps equal to the difference in exponents Set the exponent of the result equal to the larger exponent Perform addition/subtraction on the mantissas and determine the sign of the result Normalize the resulting value, if necessary

 Multiply Rule Add the exponents and subtract 127. Multiply the mantissas and determine the sign of the result Normalize the resulting value, if necessary Divide Rule Subtract the exponents and add 127. Divide the mantissas and determine the sign of the result Normalize the resulting value, if necessary.

Implementing floating-point operations

Implementing floating-point operations

Addition/Subtraction Shift-count value, n, is determined by the 8-bit subtractor circuit The magnitude of the difference EA AB, or n, is sent to the SHIFTER unit The sign of the difference that results from comparing exponents determines which mantissa is to be shifted. Step 1 The sign is sent to the SWAP network. If the sign is 0, then EA EB and the mantissas MA and MB are sent straight through the SWAP network. This results in M B being sent to the SHIFTER, to be shifted n positions to the right.

Implementing floating-point operations - Contd

The other mantissa, MA, is sent directly sent to the mantissa adder/subtractor. If the sign is 1, then EA < EB and the mantissas are swapped before they are sent to the SHIFTER. Step 2 Two-way multiplexer, MUX The exponent of the result, E, is tentatively determined as EA if EA EB, or EB if EA < EB, based on the sign of the difference resulting from comparing exponents in Step 1.

Implementing floating-point operations - Contd

Step 3 - Mantissa adder/subtractor The CONTROL logic determines whether the mantissas are to be added or subtracted. The CONTROL logic also determines the sign of the result, SR. If A is negative, B is positive, and the operation is AB, then the mantissas are added and the sign of the result is ve. If A and B are both positive and the operation is A-B, then the mantissas are subtracted. The sign of the result, SR, now depends on the mantissa subtraction operation.