Real World FPGA Design With Verilog

Real World
FPGA design
with
Verilog
Milo Milovanovi miloshm@yahoo.com Jovan Popovi josars@galeb.etf.bg.ac.yu Veljko Milutinovi vm@etf.bg.ac.yu
Literature
- Real World FPGA Design with Verilog by Ken Coffman, Prentice Hall PTR - On-line Verilog HDL Quick Reference Guide by Stuart Sutherland titan.etf.bg.ac.yu/~gvozden/VLSI/
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Field Programmable Gate Array design Verilog designed as a simulation and test language Real World - &!!! #$%&@#$%
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A day in the life of an FPGA Silicon Designer
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Design must be:

Understandable to other designers Logically correct Perform under worst-case conditions of temperature and process variation
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Design must be:

Reliable Testable and can be proven to meet the specification Do not exceed the power consumption goals (a battery-operated circuit)
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Understandable Design
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FPGA Architecture
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Xilinx 4K Family CLB Architecture
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Trivial Overheat Detector Example

josars@galeb.etf.bg.ac.yu Big Brother vm@etf.bg.ac.yu
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Solution:
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Simulation
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Assignments
Concurrent Initial: A=B=C=E=1 A <= B + C; D <= A + E; After assignment: A=2, D=2 Milo Milovanovi Sequential Initial: A=B=C=E=1 A = B + C; D = A + E; After assignment: A=2, D=3
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Module
the building block
module module_name (port_name, port_name, ... ); module_items endmodule module module_name (.port_name (signal_name ), .port_name (signal_name ), ... ); module_items Milo Milovanovi 16 /75 endmodule
Module Port Declarations

port_direction [port_size] port_name, port_name, ... ; port_direction input, output, inout port_size is a range from [ msb : lsb ] Example1: Example2: parameter word = 32; input [15:12] addr; input [word-1:0] addr;
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Data Type Declarations 1

register_type [size] variable_name , variable_name , ... ; register_type [size] memory_name [array_size]; register_type: reg - unsigned variable of any bit size integer - signed 32-bit variable time - unsigned 64-bit variable real or realtime - double-precision floating point variable Milo Milovanovi
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net_type [size] #(delay) net_name , net_name , ... ; net_type: wire or tri - Simple Interconnecting Wire wor or trior - Wired outputs OR together wand or triand - Wired outputs AND together
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#delay or #(delay) - Single delay for all output transitions #(delay, delay) - Separate delays for (rising, falling) transitions
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- wire a, b, c; - tri [7:0] data_bus; - reg [1:8] result; // an 8-bit
// unsigned variable - reg [7:0] RAM [0:1023]; 8-bits wide, with 1K of addresses - wire #(2.4,1.8) carry;a net with rise, fall delays
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Assign statement
Continuous (combinational) logic - net_type [size] net_name;
assign #(delay) net_name =

expression;
- net_type [size] net_name = expression; assign out = in1 & in2; assign bidir = OE ? out : 1 bz;
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Procedural Blocks
type_of_block @(sensitivity_list) statement_group: group_name local_variable_declarations timing_control procedural_statements end_of_statement_group
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Type of block
initial always process statements one time process statements repeatedly
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Sensitivity list
OPTIONAL Signals Posedge rising-edge triggered Negedge falling-edge triggered example: always @ (posedge clk or posedge rst) begin end
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Statement group
begin end the sequential block
fork join statements are evaluated concurrently
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Example
initial fork #10 bus = 16'h0000; #20 bus = 16'hC5A5; #30 bus = 16'hFFAA; join
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Example
always begin #10 bus = 16'h0000; #20 bus = 16'hC5A5; #30 bus = 16'hFFAA; end
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Example
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Verilog Hierarchy
module_name instance_name(port_list);
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Named & Positional Assignment
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Built-in Logic Primitives

and, or, nand, nor, xor, nxor bufif0, bufif1, notif0, notif1
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Latches and Flipflops

Clocked D flipflop
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Basic Latch
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test_out2 <= 0;
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Blocking and Nonblocking Assignments
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Blocking assignments are order sensitive
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Nonblocking Assignment
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Miscellaneous Verilog Syntax Items

Numbers
default: 32 bits wide size base value underscore is legal X is undefined Z is the high impedance
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Number examples
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Forms of Negation
! logical negation
~ - bitwise negation
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Forms of AND
& is a bitwise AND && is a logical AND (true/false)
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Forms of OR
| is a bitwise OR || is a logical OR (true/false)
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AND/OR examlpe
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Equality Operators
== is logical equality have an unknown (x) result if any of the compared bits are x or z === is case equality looks for exact match of bits including x s and z s and return only true or false
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Not equal operators

!= opposite to == !== opposite to ===
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Also supported
greater than (>) less than (<) greater than or equal (>=) less than or equal (<=)
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Shift operators
>> n << n right shift (divide by 2n) left shift (multiple by 2n)
Operating on a value which contains an x or z gives an x result in all bit positions.

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Shift operations example
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Conditional Operator
out <= expression ? true_assignment : false_assignment;
- Special case: expression = x or z

calculates every single bit
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Math Operators
addition (+), subtraction (-), multiplication (*), division (/), modulus (%) synthesis tool probably limits multiplication and division to constant powers of two verilog assumes all reg and wire variables are unsigned
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Parameters
used in modules where they are defined can be changed by higher-level modules cannot be changed at run time
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Concatenations
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Programming Statements
if, case casez, casex forever, repeat(number), while, for initial begin clk = 0; #1000 forever #25 clk = ~clk; end
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Testing
Compiler directives:
define, ifdef, else, endif, undef include timescale unit/precision example: timescale 1ns/0.5ns
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System Tasks
starts with $ $finish $stop terminate (time out)
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System Tasks
$display(format, vars ) - printf $write(format, vars ) - $display + \n $timeformat $time
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System Tasks
$monitor (signal list and formatting) $monitoron $monitoroff
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System Tasks
$dumpfile( filename ) $dumpvars $dumpall $dumpvars( ) $dumplimit(size)
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System Tasks
$readmemh( filename , memory_name) $readmemb( filename , memory_name)
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Watch for those alligators!
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Real World
FPGA design
with
Verilog
Milo Milovanovi miloshm@yahoo.com Jovan Popovi josars@galeb.etf.bg.ac.yu Veljko Milutinovi vm@etf.bg.ac.yu

Real World FPGA Design With Verilog

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Real World

Milo Milovanovi miloshm@yahoo.com Jovan Popovi josars@galeb.etf.bg.ac.yu Veljko Milutinovi vm@etf.bg.ac.yu

A day in the life of an FPGA Silicon Designer

Design must be:

Design must be:

Xilinx 4K Family CLB Architecture

Trivial Overheat Detector Example

the building block

Module Port Declarations

Data Type Declarations 1

Data Type Declarations 2

Data Type Declarations 3

Data Type Declarations 4

assign #(delay) net_name =

fork join statements are evaluated concurrently

Named & Positional Assignment

Built-in Logic Primitives

Latches and Flipflops

Blocking and Nonblocking Assignments

Blocking assignments are order sensitive

Miscellaneous Verilog Syntax Items

Not equal operators

Operating on a value which contains an x or z gives an x result in all bit positions.

Shift operations example

- Special case: expression = x or z

Watch for those alligators!

Milo Milovanovi miloshm@yahoo.com Jovan Popovi josars@galeb.etf.bg.ac.yu Veljko Milutinovi vm@etf.bg.ac.yu

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