Sequential circuit blocks

Design examples: 1) Reaction timer 2) Ring counter 3) Linear-feedback shift register

Functionality of reaction timer

To measure the reaction time of a person to a specific event.

the circuit turns on a LED. In response to the LED being turned on, the person attempts to press a switch as quickly as possible. The circuit measures the elapsed time from when the LED is turned on until the switch is pressed.

Specifications

Available clock: 102.4 kHz Resolution of time measurement: 1/100 second Two-digit BCD display: 00/100 to 99/100 second Assume that a signal w is used to turn on the LED. Push-button switch is depressed by a person to generate a signal to turn off the LED. A counter will count the time between turn-on and turn-off.

100 Hz clock
100 Hz c9 c1 c0

clock 102.4 KHz

10-bit counter

The complete timer circuit

LEDn pushn

Digit1

Digit0

c9

reset

Verilog code: 7-segment code

7-segment code
module seg7 (bcd, leds); input [3:0] bcd; output [1:7] leds; reg [1:7] leds; always @(bcd) case (bcd) //abcdefg 0: leds = 7'b1111110; 1: leds = 7'b0110000; 2: leds = 7'b1101101; 3: leds = 7'b1111001; 4: leds = 7'b0110011; 5: leds = 7'b1011011; 6: leds = 7'b1011111; 7: leds = 7'b1110000; 8: leds = 7'b1111111; 9: leds = 7'b1111011; default: leds = 7'bx; endcase endmodule

seg7

BCD code

Combinational circuit

Two-digit BCD counter

Function: output 2 four-bit signal BCD1 and BCD0 clear synchronous reset for both digits E=1 count on positive clock edge E=0 count value is unchanged.

BCD1 clear E clock BCD counter BCD0

Verilog code: BCD counter

module BCDcount (Clock, Clear, E, BCD1, BCD0); input Clock, Clear, E; output [3:0] BCD1, BCD0; reg [3:0] BCD1, BCD0; always @(posedge Clock) begin if (Clear) begin BCD1 <= 0; BCD0 <= 0; end else if (E) if (BCD0 == 4'b1001) begin BCD0 <= 0; if (BCD1 == 4'b1001) BCD1 <= 0; else BCD1 <= BCD1 + 1; end else BCD0 <= BCD0 + 1; end endmodule

Verilog code: reaction timer

module reaction (c9, Reset, w, Pushn, LEDn, Digit1, Digit0); input c9, Reset, w, Pushn; output LEDn; output [1:7] Digit1, Digit0; wire LEDn; wire [1:7] Digit1, Digit0; reg LED; wire [3:0] BCD1, BCD0;

pushn
always @(posedge c9) begin if (Pushn == 0) LED <= 0; else if (w) LED <= 1; end assign LEDn = ~LED; BCDcount counter (c9, Reset, LED, BCD1, BCD0); seg7 seg1 (BCD1, Digit1); seg7 seg0 (BCD0, Digit0); endmodule

Simulation

W (rising)LED on counting Person pushed the button stop counting LED off Display the elapsed time (result of counting)

a f e d

b c

Digit1: abc_defg Digit0: abc_defg 1: 011_0000 2: 110_1101 Common cathode

Ring counter

4-bit ring counter Q0Q1Q2Q3: 100001000010000110000100

Verilog code for ring counter

module ripplen (Resetn, Clock, Q); parameter n = 8; input Resetn, Clock; output [n-1:0] Q; reg [n-1:0] Q; always @(posedge Clock) if (!Resetn) begin Q[7:1] <= 0; Q[0] <= 1; end else Q <= {{Q[6:0]}, {Q[7]}}; endmodule

Linear-feedback shift register

D Q

D Q

q0
clock

q1

D Q

q2

Generates a sequence of pseudo-random numbers

Linear-feedback shift register

module lfsr(r,L,clock,q); input [0:2] r; input L, clock; output [0:2] q; reg [0:2] q; always @ (posedge clock) if(L) q <= r; else q <= {q[2], q[0]^q[2], q[1]}; endmodule

quiz
module lfsr2(r,L,clock,q); input [0:2] r; input L, clock; output [0:2] q; reg [0:2] q;

always @ (posedge clock) if(L) q <= r; else q <= {q[2], q[0], q[1]^q[2]}; endmodule
1. Draw the circuit using D-flip flips, multiplexers, and xor gate(s) 2. What is the sequence after loading r=001?