Seminar on

Maximum and Minimum delay constraints

Presented by
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Richa Singh

8 May 2012

Contents
1)Introduction 2)Sequencing elements timing notations 3)Sequential delays 4)Max-delay-constraints 5)Min-delay-constraints 6)Schematic diagram 7)Timing simulation 8)References

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Introduction
In sequential circuits output depends upon previous

as well as current input. Such circuits said to have a state. Sequential circuits are usually designed with flipflops and latches,which are called memory elements,that holds the data called tokens. Sequencing elements delay tokens that arrives too early,preventing them from catching up with previous tokens. Unfortunately they add some delay to the tokens that are already critical,decreasing the performance of the system. 8 May 2012

Sequencing Elements Timing Notation

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Sequential delays

Fig:1

In the above figure combinational logic input A changing from one arbitrary value to another Output can not change instantaneously,after a contamination delay tcd,Y may begin to change. After a propagation delay tpd,Y must have settled to a final value.
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Sequential delays contd

Above figure shows response of a flip flop,data input is stable for some window around the rising edge of the flip flop Data input must have settled by some setup time tsetup before the rising edge of the clk. And should not change again until a hold time thold after the clk edge.
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Fig:2

Sequential delay contd.

The output begins to change after clock to Q

contaminiation delay tccq and completely settles after clock to Q propagation delay tppq.

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Sequential delay contd

Fig:3

Above figure shows response of a latch . D must be setup and hold around the falling edge that defines end of the sample period. Output initially changes tccq after the latch become transparent on the rising edge of theMay 2012 8 clock and settles by tpcq.

Sequential delay contd

While the latch is transparent,the output will

continue to track the input after some D to Q delay tcdq and tpdq.

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Max-Delay constraints

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If the combinational logic delay is too long,the receiving element will miss its setup time and sample the wrong value. This is called max-delay-failure. The above figure shows max-delay-timing 8 May 2012 constraints on the path from flip-flop to other.

Fig:4

Max-delay-constraints contd.
The path begins with the rising edge of the

clock triggering F1. The data must propagate to the output of the flip-flop Q1and through the combinational logic to D2,setting up at F2 before next rising clock edge. The clock peroid t be T t must t atleast
c pcq pd setup

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Max-delay-constraints contd.
Max allowable logic delay

t pd Tc (t setup t pcq )
Where(t setup t pcq ) overhead is sequencing

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Min-delay constraints

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If hold time is too large and contamination delay is small,data can incorrectly propagate through two successive elements on one clk edge 8 May 2012

Fig:5

Min-delay constraints contd

Corrupting the state of the system.

This is called Race condition or min-delay-failure.

In the fig the path begin with the rising edge of

the clock triggering F1 The data may begin to change at Q1 after a clkto-Q contamination delay. And at D2 after another logic contamination dealy. It must not reach D2 until atleast the hold time thold after the clock edge.

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Min-delay constraints cond

Min logic contamination delay

tcd t hold tccq

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Schematic diagram of counter

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Fig:6

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Timing simulation

Max-delay=5ns
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Fig:7
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REFERENCES
1)CMOS VLSI DESIGN by NEIL H.E.WESTE from pg:251to260.

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