ADVANCED MICROPROCESSORS

Session 24 Prof. Venkataramaiah. P. P HEAD Department of Instrumentation Technology & Medical Electronics M.S.Ramaiah Institute of Technology, Bangalore

Topics to be covered
Session 24 : 22/11/2005 : Interrupt Processing, Interrupt Vector table, Hardware Interrupts. Expanding the Interrupt Structure Interrupt Applications

Session 25 : 23/11/2005 : Session 26 : 25/11/2005 :

INTERRUPT
The meaning of interrupts is to break the sequence of operation.While the cpu is executing a program,on interrupt breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).After executing ISR , the control is transferred back again to the main program.

Purpose of Interrupts
Interrupts are particularly useful when interfacing I/O devices that provide or require data at relatively low data transfer rate.

Interrupt Sources
Hardware Interrupts (External Interrupts) ex: NMI, INTR Software Interrupts (Internal Interrupts and Instructions) ex: INT n (Software Instructions)

8086 Interrupt Response

Mainline Program PUSH Flags CLEAR IF , TF PUSH CS PUSH IP FETCH ISR ADDRESS POP IP POP CS POP FLAGS ISR procedure PUSH registers POP registers IRET

1. It decrements SP by 2 and pushes the flag register on the stack. 2. Disables INTR by clearing the IF. 3. It resets the TF in the flag Register. 4. It decrements SP by 2 and pushes CS on the stack. 5. It decrements SP by 2 and pushes IP on the stack. 6. Fetch the ISR address from the interrupt vector table.

Interrupt Vector Type 4 POINTER Table 010H

00CH 008H 004H 000H

(OVERFLOW) Type 3 POINTER (BREAK POINT) Type 2 POINTER (NON-MASKABLE) Type 1 POINTER (SINGLE STEP) Type 0 POINTER (DIVIDE ERROR) CS base address IP offset

16 bits

03FFH 03FCH

Type 255 (Available) Available Interrupts Type 32 (Available) (224)

080H 07FH

Type 31 (Reserved) Reserved Interrupts (27) Type 5 Reserved

0014H

Interrupt Vector Table

INT Number INT 00 INT 01 INT 02 : : INT FF Physical Address 00000 00004 00008 : : 003FC

Example
Find the physical address in the interrupt vector table associated with a) INT 12H b) INT 8H Solution: a) 12H * 4 = 48H Physical Address: 00048H ( 48 through 4BH are set aside for CS & IP) b) 8 * 4 = 20H Memory Address : 00020H

Difference between INT and CALL instructions

S.No CALL
1.

INT

Can Jump to any Goes to fixed memory location with in 1MB location in the interrupt address range vector table to get address of ISR Used by the programmer in the sequence of instructions in the program Externally activated hardware interrupt can come at any time

2.

S.No CALL
3. 4. Cannot be masked (disabled) Automatically saves CS: IP of next instruction RET is the last instruction

INT
INTR can be masked In addition to CS:IP, Flags can be saved IRET to pops of F, CS:IP

5.

Functions associated with INT00 to INT04 (Exceptions)

INT 00 (divide error) INT00 is invoked by the microprocessor whenever there is an attempt to divide a number by zero ISR is responsible for displaying the message Divide Error on the screen

Ex1: Mov AL,82H ;AL= 82 SUB CL,CL ;CL=00 DIV CL ;82/0 = undefined result EX2: Mov AX,0FFFH; AX = FFFFH Mov BL,2 ; BL=02 DIV BL ; 65,535/2 = 32767 larger than 255 maximum capacity of AL

INT 01
For single stepping the trap flag must be 1 After execution of each instruction, 8086 automatically jumps to 00004H to fetch 4 bytes for CS: IP of the ISR The job of ISR is to dump the registers on to the screen

Resetting TF (TF = 0)
First method: PUSH F POP AX AND AX, 1111 1110 1111 1111 B PUSH AX POP F

Second method: PUSH F MOV BP,SP AND 0(BP), OFE FFH POP F

Setting TF (TF = 1)
Use OR instruction in place of AND instruction. PUSH F POP AX OR AX, 0000 0001 0000 0000 B PUSH AX POP F

INT 02 (Non maskable Interrupt)

8086
5v

NMI

When ever NMI pin of the 8086 is activated by a high signal (5v), the CPU Jumps to physical memory location 00008 to fetch CS:IP of the ISR assocaiated with NMI

INT 03 (break point)

A break point is used to examine the cpu and memory after the execution of a group of Instructions.

It is one byte instruction whereas other instructions of the form INT nn are 2 byte instructions.

There is an instruction associated with this INT 0 (interrupt on overflow). If INT 0 is placed after a signed number arithmetic as IMUL or ADD the CPU will activate INT 04 if 0F = 1. In case where 0F = 0 , the INT 0 is not executed but is bypassed and acts as a NOP.

INT 04 ( Signed number overflow)

Example
Mov AL , 64 Mov BL , 64 ADD AL , BL INT 0 ; 0F = 1
0100 0000 0100 0000 1000 0000 +64 +64 +128

INT 0 causes the cpu to perform INT 04 and jumps to physical location 00010H of the vector table to get the CS : IP of the ISR

HARDWARE INTERRUPTS
NMI : Non maskable interrupts INTR : Interrupt request
NMI INTR INTA 8086

Edge triggered Input Level triggered Input

Response to INTR input

Hardware Interrupts

NMI: TYPE 2 Interrupt INTR: Between 20H and FFH