AGEN DA

1. Overview of 8051 Architecture, Timing, On-chip Resources, Instruction Set etc. Derivative products 2. Programming the 8051: Basic techniques, tips & tricks.

3. Development Support: Development Boards, Emulators, EPROM Programmers, Compilers, etc.

4. I2C, a simple Multi-master 2-wire serial bus. 5. ACCESS.Bus, an I2C-based protocol for connecting peripherals to workstations/PCs.

THE 8051
An 8-bit Microcontroller optimized for control applications.

A Microcontroller derivative family based on the 8051 core.

A Microcontroller because you can make a one-chip system with the one chip containing: Program & Data Memory I/O Ports Serial Communication Counters/Timers Interrupt Control logic A-to-D and D-to-A convertors & so on ...

FEATURES OF THE 8051

- 8 Bit data path and ALU. - Easy interfacing. - 12 to 30 MHz versions available. ( 1 sec to 400 ns for single cycle instructions). - Full instruction set including: Multiply and Divide. Bit set, reset, and test (Boolean instructions). - Variety of addressing modes.

FEATURES OF THE 8051 (CONT'D)

- 4K X 8 ROM - Program memory. - 128 x 8 RAM - Data memory. - Special function registers. - Serial I/O port. - 32 I/O lines. - Two 16-bit counter/timers.

8051 LOGIC SYMBOL

VS S XTAL1 VCC RS T P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P O R T 0 ADDRES S AND DATA BUS

XTAL2

EA PS EN ALE P O R T 1

SECONDARY FUNCTIONS

RxD TxD INT0 INT1 T0 T1 WR RD

P O R T 3

P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0

P O R T 2

ADDRES S BUS

External Interrupts

80C51 BLOCK DIAGRAM

4k byte ROM 128 byte RAM Timer 1 Timer 0 Counter Inputs

Interrupt Control

CPU

OSC

Bus Control

I/O Ports

Serial Port

TXD RXD

P0 P2
(Address/Data)

P1

P3

ADDRESSING SPACE
- 64K X 8 ROM - Program memory. - 64K x 8 RAM - External data memory. - 256 x 8 RAM - Internal data memory. - 128 x 8 Special function registers (SFRs). - Bit addressing of 16 RAM locations and 16 SFRs.

PROGRAM MEMORY
- 16 bit Program Counter (PC). - 16 bit Data Pointer (DPTR). - 64K byte address space each for Program & Data. - Table lookup using relative addressing: PC + ACC (Move). DPTR + ACC (Move and jump). - EA pin disables internal ROM and

activates external program memory and addressing.

INTERNAL DATA MEMORY

- 128 bytes of RAM.
- Directly addressable range: 00 to 7F hexadecimal. - Indirectly addressable range: 00 to FF hexadecimal. - Bit addressable space: 20 to 2F hexadecimal . - Four register banks: 00 to 1F hexadecimal.

7F 30 2F 20 1F 20 17 18 0F 08

INTERNAL DATA MEMORY END 8051 RAM

FF . . . . . . . . . F8 07 . . . . . . . . . 00 REGISTER BANK 3 REGISTER BANK 2 REGISTER BANK 1 BIT ADDRESSABLE

07 R7

R6 R5 R4 R3 R2 R1
00 R0

REGISTER BANK 0

EXTERNAL DATA MEMORY

- 64K byte address space. - Indirectly addressable via R0 and R1 in 256 byte segments. - Entire space is indirectly addressable via the data pointer DPTR.

8051 PORT 2

EXTERNAL BUS EXPANSION

A15 - A8: High byte of address AD7 - AD0: Data and low byte address ALE P3.7 P3.6 ALE: Address latch enable RD: Read strobe WR: Write strobe PSEN: Program store enable

PORT 0

PSEN

8051 TIMING
State 1 State 2 State 3 State 4 State 5 State 6 State 1 State 2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 XTAL2

ALE _____ PSEN

P0

PCL out Data sampled

PCL out Data sampled PCH out PCH out

PCL out Data sampled

P2

EXTERNAL PROGRAM MEMORY

8051 PORT2 ALE AD7 - AD0 PORT0 A15 - A8 ROM(S)

ADDRESS
LATCH ADDRESS INPUTS

A7 - A0 D7 - D0
PSEN

DATA

OUTPUTS OE

 64K byte adress space. in 256 byte segments.

EXTERNAL DATA MEMORY

via the data pointer DPTR.

Indirectly addressable via R0 and R1 Entire space in indirectly addressable

8051 PORT 2 ALE PORT 0

RAM(S) or I/O DECODE CE ADDRESS INPUTS DATA OUTPUTS R/W OE

ADDRESS LATCH

WR RD

 RST pin is Schmitt trigger input.

External reset is asychronous to the internal clock. RST pin must be high for at least two machine cycles while the oscillator is running. Internal RAM not affected by reset, but indeterminate on power up. Port pins in random state until oscillator starts and algorithm write 1's to them. Reset sets PC to 0000. Typical circuits:

RE SE T

+5V

+5V

8051
10uF 2.2uF

80C51
RST

RST
8.2K

SPECIAL FUNCTION REGISTER SPACE

- 128 byte address space, directly

addressable as 80 to FF hex.
- 16 addresses are bit addressable: Set, Clear, AND, OR, MOV (those ending in 0 or 8). - This space contains: Special purpose CPU registers. I/O control registers. I/O ports.

Bit Addressable

SPECIAL FUNCTION REGISTER MAP

B ACC PSW

F8 F0

E8
E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD TL0 SP DPH TL1 DPL TH0 TH1 PCON SBUF

CPU registers: - ACC -B - PSW - SP - DPTR

SPECIAL FUNCTION REGISTERS

: Accumulator. : B register. : Program Status Word. : Stack Pointer. : Data Pointer (DPH, DPL).

Interrupt control: -IE -IP I/O Ports: - P0 - P1 - P2 - P3

: Interrupt Enable. : Interrupt Priority.

: Port 0. : Port 1. : Port 2. : Port 3.

SPECIAL FUNCTION REGISTERS

(CONT'D) TImers: - TMOD : Timer mode.

- TCON
- TH0 - TL0 - TH1 - TL1 Serial I/O: - SCON - SBUF

: Timer control.
: Timer 0 high byte. : Timer 0 low byte. : Timer 1 high byte. : Timer 1 low byte.

: Serial port control. : Serial data registers.

Other:
- PCON : Power control & misc.

PSW : PROGRAM STATUS WORD

CY AC
- CY

F0

RS1
: Carry Flag.

RS0

OV

----

- AC : Auxiliary Carry Flag. - F0 : Flag 0 (available for user). - RS1 : Register Select 1. - RS0 : Register Select 0. - OV : Arithmetic Overflow Flag. -P : Accumulator Parity Flag.

RS1 0 0

RSO 0 1

Register Bank 0 1

Address 00h - 07h 08h - 0Fh

1
1

0
1

2
3

10h - 17h
18h - 1Fh

I/O PORT - Four 8-bit I/O ports. S

- Most have alternate functions. - Quasi-bidirectional: Soft pull-up when port latch contains a 1. Can be used as inputs (30Kohm average pullup). Strong pull-up for 2 CPU cycles during 0 to 1 transitions.

CONFIGURAT ION
CMOS
2 OSC. PERIODS

V C C

VC C

VC C

P1

P2

P3 PORT PIN

Q FROM PORT LATCH

N INPUT DATA READ PORT PIN

NMOS
2 OSC. PERIODS

PORT PIN Q FROM PORT LATCH

- As an I/O port:
open drain.

PO RT 0

No strong pull-up, outputs act as

- As a multiplexed data bus: Tristate bus with strong pull-ups. 8-bit instruction bus, strobed by PSEN. Low byte of address bus, strobed by ALE. 8-bit data bus, strobed by WR and RD. - 3.2 mA outputs (about 8 LSTTL loads).

As an I/O port:

PO RT 1

Standard quasi-bidirectional.

- Alternate functions:
Only on some derivatives.

- 1.6 mA outputs (about 4 LSTTL loads).

- As an I/O port:

PO RT 2

Standard quasi-bidirectional.

- Alternate functions: High byte of address bus for external program and data memory accesses.

- 1.6 mA outputs (about 4 LSTTL loads).

PO RT - As an I/O port: 3
Standard quasi-bidirectional. - Alternate functions: Serial I/O Timer clocks Interrupts Data memory - TXD, RXD - T0, T1 - INT0, INT1 - RD, WR

- 1.6 mA outputs (about 4 LSTTL loads).

COUNTER / TIMERS
- Two 16-bit Counter/Timers:
Up counters, can interrupt on overflow. - Counts:

CPU cycles (crystal/12).

External input (max. half CPU rate). - Four Operation Modes.

TIMER MODES - Timer Mode 0 :

Emulates 8048 counter/timer (13-bits). 8-bit counter (TL0 or TL1). 5-bit prescaler (TH0 or TH1). - Timer Mode 1 : Simple 16-bit counter. - Timer Mode 2 :

8-bit auto-reload. Counter in TL0 or TL1. Reload value in TH0 or TH1. Provides a periodic flag or interrupt.

TIMER MODES - Timer Mode 3 :

(CONT'D)

Splits timer 0 into two 8-bit counter/timers. First counter (TLO) acts like mode 0, without prescaler. Second counter (TH0): Counts CPU cycles. Uses TR1 (timer 1 run bit) as enable. Uses TF1 (timer 1 overflow bit) as flag. Uses Timer 1 interrupt. Timer 1 (when timer 0 is in mode 3 ): Counter stopped if in mode 3. Running in mode 0, 1, or 2. Has gate (INT1) and external input (T1), but no flag or interrupt. May be used as a baud rate generator.

COUNTER/TIMER IN 16-BIT (MODE 1)

Osc. 12

I nt er r upt TL1 T1 (Pi n) TR1 TH1

8- bits 8- bits

TF1

Cont r ol

Gat e

I NT1 (Pi n)

The Gate input controls whether the Counter runs while gated by the interrupt signal or not.

TMOD : COUNTER/TIMER MODE REGISTER

GATE C/T M1 Timer 1 M0 GATE C/T M1 Timer 0 M0

- GATE : Permits INTx pin to enable/disable counter. - C/T : Set for counter operation, reset for timer operation.

- M1, M0 :
00 : Emulate 8048 counter/timer (13-bits). 01 :16-bit counter/timer. 10 : 8-bit auto-reload mode 11 :Timer 0 = two 8-bit timers.

Timer 1 Counting disabled. Timing function allowed. Can be used as Baud Rate generator.

TCON : COUNTER/TIMER CONTROL REGISTER

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
- TF1, TF0 : Overflow flags for Timer 1 and Timer 0. - TR1, TR0 : Run control bits for Timer 1 and Timer 0. run, reset to hold. Set to

- IE1, IE0 : Edge flag for external interrupts 1 and 0. * Set by interrupt edge, cleared when interrupt is processed. - IT1, IT0 : Type bit for external interrupts. * Set for falling edge interrupts, reset for 0 level interrupts. * = not related to counter/timer operation.

SERIAL INTERFAC - Full duplexE UART.

- Four modes of operation: Synchronous serial I/O expansion. Asynchronous serial I/O with variable baud rate. Nine bit mode with variable baud rate. Nine bit mode with fixed baud rate. - 10 or 11 bit frames. - Interrupt driven or polled operation. - Registers: SCON - Serial port control register. SBUF - Read received data. - Write data to be transmitted. PCON - SMOD bit.

SERIAL INTERFACE MODES OF OPERATION

TXD and RXD are the serial output and input pins (Port 3, bits 1 and 0).

Mode 0: Shift Register Mode. Serial data is transmitted/received on RXD. TXD outputs shift clock. Baud
Rate is 1/12 of clock frequency. Mode 1: 10-bits transmitted or received. Start (0), 8 data bits (LSB first), and a stop bit (1). Baud Rate Clock is variable using Timer 1 overflow or external count input. Can go up to 104.2KHz (20MHz osc.). Mode 2: 11-bits transmitted or received. Start (0), 8 data bits (LSB first), programmable 9th bit, and stop bit (1). Baud Rate programmable to either 1/32 or 1/64 oscillator frequency (625KHz for 20MHz osc.). Mode 3: 11-bit mode. Baud Rate variable using Timer 1 overflow or external input. 104.2 KHz max. (20 MHz osc.).

MULTI-DROP COMMUNICATION
Serial Communication Modes 2 and 3 allow one "Master" 8051 to control several "Slaves": The serial port can be programmed to generate an interrupt if the 9th data bit = 1. The TXD outputs of the slaves are tied together and to the RXD input of the master. The RXD inputs of the slaves are tied together and to the TXD ouput of the master. Each slave is assigned an address. Address bytes transmitted by the master have the 9th bit = 1. When the master transmits an address byte, all the slaves are interrupted. The slaves then check to see if they are being addressed or not. The Addressed slave can then carry out the master's commands.

SCON : SERIAL CONTROL REGISTER

SMO SM1 SM2 REN TB8 RB8 TI RI
- SM0, SM1 = Serial Mode: 00 = Mode 0 : Shift register I/O expansion. 01 = Mode 1 : 8-bit UART with variable baud rate. 10 = Mode 2 : 9-bit UART with fixed baud rate. 11 = Mode 3 : 9-bit UART with variable baud rate. - SM2 : Mode 0 : Not used. Mode 1 : 1 = Ignore bytes with no stop bit. Mode 2,3 : 0 = Set receive interrupt (RI) on all bytes. : 1 = Set RI on bytes where bit 9 = 1. - REN = Enables receiver. - TB8 = Ninth bit transmitted (in modes 2 and 3). - RB8 = Ninth bit received: Mode 0 : Not used. Mode 1 : Stop bit. Mode 2,3 : Ninth data bit. - TI = Transmit interrupt flag. - RI = Receive interrupt flag.

INTERRUPT SYSTEM
- 5 Interrupt Sources (in order of priority): External Interrupt 0. Timer 0. External Interrupt 1. Timer 1. Serial Port. - Each interrupt type has a separate vector address. - Each interrupt type can be programmed to one of two priority levels.

- External interrupts can be programmed for edge or level sensitivity.

IE : INTERRUPT ENABLE REGISTER

EA ------ES ET1 EX1 ET0 EX0 - EA - ES - ET1 - EX1 - ET0 - EX0 : Global interrupt enable. : Serial interface. : Timer 1. : External interrupt 1. : Timer 0. : External interrupt 0. - 0 = Disabled. - 1 = Enabled.

INTERRUPT VECTOR ADDRESSES

Source IE0 TF0 IE1 TF1 RI&TI Address 03H 0BH 13H 1BH 23H

The 8051 starts execution at 0000H after Reset.

IP: INTERRUPT PRIORITY REGISTER

------------PS PT1 PX1 PT0 PX0

- PS

: Serial interface.

- PT1
- PX1 - PT0 - PX0

: Timer 1.
: External interrupt 1. : Timer 0. : External interrupt 0. 0 = Low priority. 1 = High priority.

80C51(CMOS) VS. 8051(NMOS)

Controlled Power Reduction Idle State Power down state Power savings in CMOS ports

General purpose software flags

Higher speed versions in 80C51 (up to 30MHz) Static versions in development

PCON : POWER CONTROL REGISTER

SMOD ---------GF1 GF0 PD IDL

- POWER DOWN OPERATION Setting PD bit stops oscillator. RAM contents are saved. Exit via Reset. Some (newer) 80C51 derivatives allow Power-Down wakeup via Interrupt.

PCON : POWER CONTROL REGISTER

- IDLE MODE OPERATION Setting IDL gates clocks off, leaves oscillator running. All register and RAM contents are saved.

Interrupt sources remain active: Serial interface. External interrupts. Timers. Exit with any enabled interrupt or Reset. - GF0, GF1 are general purpose software flags. - SMOD serial interface control bit. Doubles baud rate in modes 1,2, and 3. - Only SMOD available on NMOS parts.

POWER CONSUMPTIO N
Example : for 80C51 at Vcc = 5V.

Mode / Freq.
Operating Idle Power Down

0.5 MHz
2.2 mA 0.9 mA 50 uA

16 MHz
20.5 mA 5.0 mA 50 uA

There are basically 5 ways of specifying source/destination operand addresses: 1. Particular On-chip Resources: This includes the Accumulator (A), the Stack Pointer (SP), the Data Pointer (DP), the Program Counter (PC), and the Carry (C). Other On-chip Registers are Memory-mapped while these have special Op-codes. 2. Immediate operands: The # sign is the designator. These are 8-bits except for DPTR contents (16-bits). 3. Register operands: Designated as Rn, where n is 0..7. One of the four Register Banks is used (PSW selected). 4. Direct Operands: From 00 to FF Hex, specifies one of the internal data addresses. 5. Indirect Address: Designated as @Ri, where i is 0 or 1, uses the contents of R0 or R1 in the selected Register Bank to specify the address. Other form is @A, using Accumulator contents.

ADDRESSING MODES

Mnemonics ADD ADDC

INSTRUCTION SET : ARITHMETIC

Operands A, Rn A, direct 1/1 2/1

Bytes/Cycles

SUBB

A, @Ri
A, #data

1/1
2/1 1/1 1/1

INC DEC

A Rn

direct
@Ri INC MUL DPTR AB

2/1
1/1 1/2 1/4

DIV
DA

AB
A

1/4
1/1

Mnemonic ANL ORL

INSTRUCTION SET : LOGIC

Operands A, Rn A, direct

Bytes/Cycles 1/1 2/1

XRL

A, @Ri
A, #data direct, A direct, #data C, bit

1/1
2/1 2/1 3/2 2/2

C, /bit
CLR CPL A C bit

2/2
1/1 1/1 2/1

INSTRUCTION SET : LOGIC (CONT'D)

Mnemonic RL RLC RR RRC SWAP SETB CLR CPL 2/1 Operands A A A A A C bit Bytes/Cycles 1/1 1/1 1/1 1/1 1/1 1/1

INSTRUCTION SET : DATA TRANSFER

Mnemonic MOV Operands A, Rn A, direct 1/1 2/1

Bytes/Cycles

A, @Ri
A, #data Rn, A Rn , direct Rn, #data direct, A direct, Rn direct, direct direct, @Ri direct, #data

1/1
2/1 1/1 2/2 2/1 2/1 2/2 3/2 2/2 3/2

INSTRUCTION SET : DATA TRANSFER

(CONT'D) Mnemonic MOV Operands @Ri, A @Ri, direct @Ri, #data DPTR, #data16 C, bit bit, C MOVX A,@DPTR @DPTR,A A,@Ri @Ri,A Bytes/Cycles 1/1 2/2 2/1 3/2 2/1 2/2 1/2 1/2 1/2 1/2

INSTRUCTION SET: DATA TRANSFER (CONT'D)

Mnemonic MOVC Operands A, @A+DPTR A, @A+PC PUSH POP XCH direct direct A, Rn A, direct A, @Ri XCHD A, @Ri Bytes/Cycles 1/2 1/2 2/2 2/2 1/1 2/1 1/1 1/1

INSTRUCTION SET : BRANCHING

Mnemonic LCALL ACALL RET RETI LJMP Operands addr16 addr11 addr16 Bytes/Cycles 3/2 2/2 1/2 1/2 3/2

AJMP
SJMP JMP JZ JNZ

addr11
rel @A+DPTR rel rel

2/2
2/2 1/2 2/2 2/2

INSTRUCTION SET : BRANCHING (CONT'D)

Mnemonic CJNE Operands A, direct, rel A, #data, rel Rn, #data, rel @Ri,#data,rel Bytes/Cycles 3/2 3/2 3/2 3/2

DJNZ

Rn, rel
direct, rel

2/2
3/2 1/1 2/2

NOP JC

rel

JNC
JB JNB JBC

rel
bit, rel bit, rel bit, rel

2/2
3/2 3/2 3/2

THE I 2C BUS
(INTER - INTEGRATED CIRCUIT) A 2 wire serial data and control bus

Implemented with one serial data (SDA) and one clock (SCL) line.
Unique start and stop conditions. Slave selection protocol uses a 7-Bit slave address. Bi-directional data transfer. Acknowledgement after each byte transferred. No limit on the number of bytes transferred. Real multimaster capability.

I2C BUS FEATURES

Clock synchronization.

Arbitration procedure.
Transmission speed up to 100Khz Maximum bus length of 4 meters. Maximum drive capacity of 400pF.

Allows series resistor for IC protection.

Compatible with most IC technologies (TTL, CMOS,Etc.).

I2C DEFINITIO NS
MASTER:
Initiates a transfer by generating start and stop conditions. Generates the clock. Transmits the slave address. Determines data transfer direction. SLAVE: Responds only when addressed.

Timing is controlled by the clock line.

I2C HARDWARE DETAILS Devices connected to the bus must have an open drain or
open collector output for serial clock and data. The device must also be able to sense the logic level on these pins. All devices must have a common reference ground.

The serial clock and data lines are connected to VCC through pull up resistors.
At any given moment the I2C bus is: Idle, in Master transmit mode, or in Master receive mode.

THE OPEN DRAIN CONFIGURATION OF I2C CIRCUITS

+VDD Pull-up Resistors SDA SCL Serial data line Serial clock line Rp Rp

SCLK1 OUT

DATA1 OUT

SCLK2 OUT

DATA2 OUT

SCLK IN

DATA IN

SCLK IN

DATA IN

DEVICE 1 I2C devices are wire ANDed together.

DEVICE 2

START AND STOP CONDITIONS

A transition of the data line, when the clock line is high, is defined as either a start or a stop condition.

Both start and stop conditions are generated by bus master. The Bus is busy after a start condition.

SDA SCL

SDA SCL P Stop Condition

S Start Condition

BIT TRANSFER ON THE I2C BUS

In normal data transfer, the data line only changes state when the clock is low.

SDA
SCL

Data line stable: Data valid

Change of data allowed

I2C ADDRE SS
Each node has a unique 7 bit address. Peripherals usually have fixed and programmable address portions.

Addresses starting with 0000 or 1111 have special functions.

0000000 is a general call address.0 a null address. reserved for future bus expansion 0000001 is 1111xxxx is

FIRST BYTE TRANSMITTED ON THE I2C BUS

MSB LSB ACK

R/W 7-bit slave address

R/W : 0 - Slave will be written by master. 1 - Slave will be read by master.

ACKNOWLE DGEMENT
Master/slave receivers pull data line low for one clock pulse after reception of a byte. Master receiver leaves data line high after receipt of the last byte requested. Slave receiver leaves data line high on the byte following the last byte it can accept.

DATA TRANSFER ON THE I2C BUS

SDA MSB SCL S START CONDITION 1 2 7 8 9 ACK 1 2 3-8 9 ACK P STOP CONDITION

POSSIBLE DATA FORMATS

Master Write:
S SLAVE ADDRESS W A DATA A DATA A P

Acknowledge from slave

Master Read:
S SLAVE ADDRESS R A DATA A DATA NA P

Acknowledge from master Acknowledge from slave No acknowledge from master

I2C CLOCK SYNCHRONIZATIO N

Clock synchronization is used to synchronize arbitrating masters. It can also be used as a handshake by a slave device to slow data transfer from a master. The clock synchronization procedure consists of two algorithms: 1) If the clockline goes low when a master is asserting a high, the master asserts a low and starts to time out its low clock period. 2) When a master stops asserting a low on the clock line, it waits until the clockline actually goes high before starting to time the high period.

I2C-BUS CLOCK SYNCHRONIZATION PROCEDURE

Wait State CLK 1 Start counting high period

CLK 2 Start counting low period

SCL

MULTIMASTER I2C SYSTEMS

Multimaster situations require two additional features of the I2C protocol. ARBITRATION: Arbitration is the procedure by which competing masters decide final control of the bus. I2C arbitration does not corrupt the data transmitted by the prevailing master. Arbitration is performed bit by bit until it is uniquely resolved. Arbitration is lost by a master when it attempts to assert a high on the data line and fails..

ARBITRATION PROCEDURE BETWEEN TWO MASTERS

Transmitter 1 loses arbitration

DATA1

DATA2

SDA

SCL

I2C FAMILY ICS

Microcontrollers Microprocessors General Purpose Peripherals I/O, Memory, Display, DAC, ADC, Clock/Calendar Peripherals for Specific Target Martkets Audio, Telephony, Video

AN OPEN DESKTOP BUS STANDARD BASED ON I2C

ACCESS.B US .1
DEC has invented an interconnect method for connecting a PC or Workstation to low speed I/O devices such as:

Keyboards Mouses Trackballs Tablets Low speed printers Modems

This interconnect method, known as ACCESS.bus, is based on the I2C serial protocol invented by Philips.

ACCESS.B US .2
ACCESS.bus features:

80 KBps Peak Bandwidth

Hot plugging and unplugging of devices (keyboard, mouse, etc.)

Up to 14 devices
Up to 8 Meters (26.4 feet) in length Serial, daisy-chained 4-pin cable (2 pins are power and ground). Only ONE device port needed on computer.

ACCESS BUS .3
ACCESS.Bus features: Layered 3-layer protocol defined by DEC: Physical layer is I2C. Base Protocol over I2C defines the structure of I2C messages and defines Control and Status Messages. Also supports auto-addressing and hot plugging. Applications Protocol defines message semantics for particular device types. Extremely low cost implementation based on off-the-shelf Microcontrollers with I2C such as the Signetics 83/87C751 (used in new DEC workstation ).

ACCESS.B US .4 Device address and type recognition is automatic. No drivers have to be loaded.
Concise protocol. Only 7 standard message types. Fully implemented in the 87C751 with 2K of Program memory. ACCESS.Bus is part of DEC's ARC and ACE platforms.

Fully open and free. No royalties.

DEC and Signetics will provide Developer's Kit with all information required to to develop applications. DEC's TRI/ADD developer program will provide technical support, documentation and updates, technical seminars, and newsletters and assist with marketing support.

ACCESS.B US is Apple's ADB (Apple Desktop Bus). The .5 The closest thing to the ACCESS.bus
following is a comparison between ADB and ACCESS.bus: ADB not recommended ACCESS.bus fully supported Hot-Plugging

Peak data rate

Daisy-chain limit

10 KBits/sec
3 devices

80 KBits/sec
14 devices

3rd party access

Max. cable length

Proprietary
5 meters

Open. No royalties
8 meters

DIRECTIONS FROM THE CORE PRODUCT

Analog-toDigital

Low Power Low Voltage

EPROM & OTP

Very Small Packages

Extended I/O

80C51

Memory 2 to 32 K

ASIC Cell Library Speed

Up to 30 MHz

EEPROM derivatives I2C Serial Bus

PHILIPS/SIGNETICS 8051 FAMILY

Product Name Process ROM 8031/51 8032/52 8XC751 8XC752 8XC31/51 8XCL410 80/3C851 8XC550 8XC451 8XC652 8XC52 8XC053/054 8XC562 8XC552 8XC654 8XC524 8XC528 NMOS NMOS 4K 8K RAM 128 256 64 64 128 128 128 128 128 256 256 256 256 256 512 512 Pins 8-bit Ports Serial I/O Timers 40 40 24 28 40 40 40 40 68 40 40 42 68 68 40 40 40 4 4 2+3/8 2+5/8 4 4 4 4 7 4 4 4 6 6 4 4 4 UART UART I2C I2C UART I2C UART UART UART UART,I2C UART -UART UART,I2C UART,I2C UART, I2C UART,I2C 2 3 1 1 2 2 2 2 2 2 3 2 4 4 2 3 3 Special Industry Standard Industry Standard 24 Pin Skinny DIP 8-bit A/D,PWM 20,24, 30MHz LowVolt/Power (1.8 volts) 256 EEPROM 8-bit A/D, WD 7 I/O Ports 8K ROM, I2C Serial Bus Industry Standard TV Display (OSD), D/A 8-bit A/D, PWM, WD, T2 10-bit A/D, PWM, WD, T2 16K ROM, I2C Serial Bus 16K, 512 bytes, WD 32K ROM, 512 RAM, WD

CEPROM 2K CEPROM 2K CEPROM 4K SACMOS EEPROM 4K 4K

CEPROM 4K CEPROM 4K CEPROM 8K CEPROM 8K CEPROM 8K CEPROM 8K CEPROM 16K CEPROM 16K CEPROM 32K

CEPROM 8K/16k 192

80C51 CODING:
IDEAS AND EXAMPLES

READING A TIMER "ON THE FLY"

ReadTimer: MOV MOV MOV CJNE SJMP ChkHigh: JB ValH,TH0 ValL,TL0 A,TH0 A,ValH,ChkHigh RTEX ValL.7,RTEX ;Read timer high byte again. ;Has it changed? ;If not, first sample is OK. ;Otherwise, check low byte to see if it ; changed after the original high byte ; sample. MOV RTEX: RET ValH,A ;If it did change, use second high byte ; sample. ;Read initial timer high and low values.

COMP ARE
The 80C51 has no basic compare instruction. However, the CJNE (compare and jump if not equal) instruction leaves the carry flag set after execution, allowing further magnitude comparisons to be made. This method works for all variations of CJNE: CJNE CJNE CJNE A,direct,rel A,#data,rel Rn,#data,rel

CJNE

@Ri,#data,rel

Examples of four variations of magnitude comparison: CJNE Test: JC CJNE Test: JNC CJNE SJMP Test: Else: JNC ----CJNE SJMP Test: JNC A,Value,Test LTE LTE ;Branch if A <= Value. A,Value,Test LT A,Value,Test GTE A,Value,Test Else GT ;Branch if A > Value. ;Branch if A >= Value. ;Branch if A < Value.

COMP ARE

Most instructions that reference 80C51 port data read the value on the port pins rather than the value in the port latch. However, some instructions read the port latch instead. 1) Arithmetic or logical operations that may alter port values: ANL port,src ORL port,src XRL port,src INC port DEC port DJNZ port,label 3) Instructions that may alter port bits: MOV bit,C JBC bit,label CPL bit CLR bit SETB bit

READMODIFYWRITE

SINGLE STEP UNDER PROGRAM CONTROL

The 80C51 does not have any specific built-in facility for allowing a hardware single step operation. However, when a Return from Interrupt instruction is executed, at least one instruction from the originally interrupted routine is always executed before another interrupt may be serviced. Thus, if execution of RETIs are carefully controlled while an interrupt is pending, a software single step may be effected.

This example uses external interrupt 0 as the means to accomplish the single step. This interrupt is a good choice because it is the highest priority interrupt . Note: the user program must not write to the IE or IP registers or make use of other interrupt related functions. ;Set up for single step of some user routine: StartSS: SETB SETB JNB JB MOV LJMP . . JNB JB RETI PX0 IT0 INT0,$ INT0,$ IE,#81h UserProg . . INT0,$ INT0,$ ;Set INT0 as high priority. ;Set INT0 to edge triggered mode. ;Wait for a "single step" interrupt to come, ; and go. ;Enable INT0 and insure that we are not ; interrupted during the following jump. ;Code to dump registers, user program ; address, etc. ;Wait for a "single step" interrupt to come, ; and go. ;This RETI will allow one user program instruction to ; execute, after which we will return to the INT0 service ; routine.

SINGLE STEP UNDER PROGRAM CONTROL

ExInt0:

PULSE WIDTH MEASUREMENT

Problem: measure the width of an input pulse.

start timer

stop timer

Assumption: use external interrupt 0 for the pulse input. Use timer 0 in gated mode.

Note: to measure pulse low time in this manner, the input must be inverted externally.

PULSE WIDTH MEASUREMENT

Setup: MOV MOV MOV MOV SETB SETB SETB . . . TMOD,#09h TCON,#01h TH0,#0 TL0,#0 TR0 EX0 EA . . . ;Timer 0 gate on, in mode 1. ;Set INT0 to edge triggered mode. ;Clear timer 0 for measurement. ;Start timer in gated mode. ;Enable external interrupt 0. ;Enable global interrupts.

;External interrupt 0 service routine. ExInt0: CLR TR0 MOV ValH,TH0 MOV ValL,TL0 MOV TH0,#0 MOV TL0,#0 SETB TR0 RETI

;Stop timer. ;Save timer value. ;Clear timer 0 for measurement. ;Restart timer.

PULSE PERIOD MEASUREMENT

Problem: measure the period of an input pulse.

start timer

stop timer

Assumption: use external interrupt 0 for the pulse input.

Note: this method may entail some loss of precision due to the possibility of variable interrupt latency.

PULSE PERIOD MEASUREMENT

Setup: (same as previous example, but leave timer gate function turned off) MOV TMOD,#01h ;Timer 0 in mode 1.

;External interrupt 0 service routine. ExInt0: CPL JB MOV MOV MOV MOV INT0EX: RETI TR0 TR0,INT0EX ValH,TH0 ValL,TL0 TH0,#0 TL0,#0 ;Clear timer so another sample can ; be taken. ;Complement the timer run flag. This starts ; and stops the timer on alternate interrupts. ;Exit if timer is running. ;Otherwise sample the timer value.

CREATING AN OUTPUT PULSE

Problem: create a pulse of known duration on a port pin.

timer

start pulse, timer

stop pulse

Assumption: use any spare port bit for the output.

Note: the precision of pulses generated using this method will vary depending on the interrupt latency of the timer interrupt.

CREATING AN OUTPUT PULSE

Setup: MOV MOV MOV number of machine width. SETB SETB TR0 P2.0 TCON,#0h TMOD,#01h TH0,#HiTime MOV ;Make sure timer is stopped. ;Set timer to mode 1. ;Load timer with pulse duration. The value is the TL0,#LoTime ; two's complement of the ; cycles to use for the pulse ;Start timer. ;Start pulse (use CLR for a low going pulse).

;Tiimer 0 interrupt routine. T0INT: CLR CLR RETI P2.0 TR0 ;End of pulse (use SETB for a low going pulse). ;Stop timer.

PROGRAMMING A PWM OUTPUT

Problem: create a PWM output on a port pin.

set timer low time

set timer high time

repeat

Note: the precision of pulses generated using this method will vary depending on the interrupt latency of the timer interrupt.

PROGRAMMING A PWM OUTPUT

T0INT: CLR CPL JB MOV MOV SJMP SetPWMHigh: MOV MOV T0EX: SETB RETI TR0 P2.0 P2.0,SetPWMHigh TH0,PWMLowH TL0,PWMLowL T0EX TH0,PWMHighH TL0,PWMHighL TR0 ;Restart timer. ;Set PWM high time. ;Stop timer. ;Toggle output bit. ;Is current phase high or low? ;Set PWM low time.

Note: for higher frequency pulses, it may be possible to use the timer reload feature (mode 2) to obtain more accurate pulse durations.

BLOCK MEMORY MOVE WITH EXTERNAL DATA MEMORY

Problem: move any random external data memory block of any length to another location. FFFF

{
{
0000

BlockMove: MOV MOV MOV MOV MOV Loop: MOVX MOVX INC INC MOV JNZ INC DJNZ DJNZ RET

R0,#LOW(FromAddr) P2,#HIGH(FromAddr) DPTR,#ToAddr R1,#LOW(ByteCount) R2,#HIGH(ByteCount) A,@R0 @DPTR,A DPTR R0 A,R0 L1 P2 R1,Loop R2,Loop

BLOCK MEMORY MOVE

;Initialize 'from' memory pointer. ;Initialize 'to' memory pointer. ;Initialize byte count.

;Read in a source block byte. ;Write byte out to destination block. ;Increment 'to' memory pointer. ;Increment 'from' memory pointer.

L1:

;Decrement byte count and ; test for end of block.

IMPLEMENTING A SECOND UART IN FIRMWARE

Often, an application may require a second UART communication function. A simplex (transmit or receive only at any one time) UART can be programmed with the use of one timer. The transmit routine will simply start the timer, create a start bit, and then send one bit at every timer interrupt, until finally sending the stop bit. The transmit bit may be any unused port bit. Since the receive routine must sample each bit somewhere in the middle of the bit cell, it starts the timer with a value of a half bit cell when a start is detected. Then, on the first timer interrupt, it verifies the presence of the start bit and changes the timer count to one full bit cell. On every subsequent timer interrupt, one data bit is read, until finally the stop bit is verified. The receive bit must be an external interrupt pin (usually INT0 or INT1).

UART FLOW: START TRANSMIT

Start Transmit

Set up timer for one bit cell time.

Get byte to be transmitted and set bit count.

Send start bit.

Exit

UART FLOW: START RECEIVE

Start Receive (START bit Interrupt)

Set bit count.

Set up timer for one half bit cell time.

Exit

UART FLOW: TIMER INTERRUPT

Timer Interrupt

Advance bit count.

Receive?

Receive One Bit

N Transmit One Bit

UART FLOW: TRANSMIT ONE BIT

Transmit One Bit

Done? N

Send STOP bit.

Rotate transmit byte and send next data bit.

Exit

UART FLOW: RECEIVE ONE BIT

Receive One Bit

First bit?
Y

Done? N

Look for STOP (set error flag and abort if not found).

Change timer setting to one full bit cell time.

Look for START (set error flag and abort if not found).

Get next data bit and rotate into received byte.

Exit

80C51 DEVELOPMENT SUPPORT

SIGNETICS/CEIBO 80C51 FAMILY DEVELOPMENT BOARD

Supports 80C51 derivative microcontrollers that have external program memory access and serial port. Connects to an MS-DOS compatible PC via serial port (PC runs user interface software). Line assembler and disassembler. Register and memory contents may be viewed and altered. Source, memory, register windows.

32K user program memory on board.

Software breakpoints.

80C51 FAMILY DEVELOPMENT BOARD

Help screens. Symbolic debugger. Upload and download of object and hex files.

(CONTINUED)

Fully documented. User's manual includes experiments for learning the development board and the 80C51 architecture. Switches, LEDs, and a potentiometer are included to allow simple experiments to be performed without additional circuitry.

SUPPORTED MICROCONTROLLE RS
Type 1 (full support via RS-232 to PC) 8031/51 8032/52 8xC31/51 8xC32/52 8xC451 8xC550 8xC552 8xC528 8xC652/654 8xC851

SUPPORTED MICROCONTROLLERS
(CONTINUED) Type 2 (limited support via I2C bus to type 1 device and PC) 8xC410 8xC751 8xC752

The 8xC751 and 8xC752 have no external program memory capability and do not support user program loading on the DB-51. The 8xC410 does not have an on-chip UART and must be communicated with via its I2C port. The current version of the DB-51 does not support user program loading on the 8xC410.

DEMO BOARD BLOCK DIAGRAM

MS -DOS Compatible PC PC S oftware (user interface)

RS -232 Interface

Type 1 Microcontroller

Emulation Memory 32K x 8 Monitor EPROM

I2C bus
Type 2 Microcontroller

USES FOR THE DEMO BOARD

Training vehicle for 80C51 product seminars. Self training and experimentation system for customers, FAEs, sales, factory, etc. Basis for product demonstrations to customers. Low cost development support, allows limited hardware and software prototyping.

EMULA TORS
Nohau Corp. 51 E. Campbell Ave. Campbell, CA 95008 (408) 866-1820 MetaLink Corp. 325 E. Elliot Road, Suite 23 Chandler, AZ 85225 (602) 926-0797 Ceibo Ltd. 105 Gleason Rd. Lexington, MA 02173 (617) 863-9927 And others... Signum Systems 171 E. Thousand Oaks Blvd., #202 Thousand Oaks, CA 91360 (805) 371-4608 BSO/Tasking 128 Technology Center P.O.Box 9164 Waltham, MA 02254-9164 (617) 894-7800

LIST OF PROGRAMMER MANUFACTURER CONTACTS

Data I/O Corporation 10525 Willows Rd. N.E. P.O. Box 97046 Redmond, WA 98073-9746 (206) 867-6899 Logical Devices, Inc. 1201 Northwest 65th Place Ft. Lauderdale, FL 33309 (305) 974-0967 Signetics Co. (contact nearest sales office) And many others... North Valley Designs 1610B Dell Avenue Campbell, CA 95008 (408) 866-4300 Needham's Electronics 4535 Orange Grove Ave. Sacramento, CA 95841 (916) 924-8037 Ceibo Ltd. 105 Gleason Rd. Lexington, MA 02173 (617) 863-9927

8051 CROSS ASSEMBLERS

Metalink macro cross assembler ASM51 Public Domain! Free on the Signetics BBS 2500 AD software Macro assembler Cross assembler Simulator / debugger And a host of others...

Archimedes Software, Inc. 2159 Union Street

8051 C COMPILERS

2500 AD Software, Inc. 109 Brookdale Avenue P.O. Box 480 Buena Vista, CO 81211 (800) 843-8144

San Francisco, CA 94123-9923

(415) 567-4010 Avocet Systems, Inc. 120 Union Street P.O. Box 490 BP Rockport, Maine 04856 (800) 448-8500 BSO/Tasking 128 Technology Center PO Box 9164 Waltham, MA 02254-9164 (617) 894-7800

Franklin Software, Inc. 888 Saratoga Ave., #2 San Jose, CA 95129 (408) 296-8051 And others...

MICROCONTROLLER SUPPORT BBS

Support for Philips/Signetics PLDs and Microcontrollers Modem 300/1200/2400 baud, 8-N-1

Download software:
- Public Domain 80C51 support tools - Demonstration code Send messages to Signetics applications engineers (800) 451-6644 or (408) 991-2406