Téléversements by kn65238859

Altera Voltage Regulator Selection for FPGAs

Altera FPGAs Enable Energy-Efficient Motor Control in Next-Generation Smart Home Appliances

Altera Crest Factor Reduction for OFDM-Based Wireless Systems

Altera Controlling Analog Output From a Digital CPLD Using PWM

Altera a Flexible Architecture for Fisheye Correction in Automotive Rear-View Cameras

Altera 40-Nm FPGAs- Architecture and Performance Comparison

Altera 40-Nm FPGA Power Management and Advantages

Altera Power-Optimized Solutions for Telecom Applications

Altera Leveraging the 40-Nm Process Node to Deliver the World's Most Advanced Custom Logic Devices

Altera Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis_Timing Constraints

Altera Developing Multipoint Touch Screens and Panels With CPLDs

Altera Selecting the Ideal FPGA Vendor for Military Programs

Altera Radiocomp Remote Radio Heads and the Evolution Towards 4G Networks

Altera Video Processing on FPGAs for Military Electro-Optical_Infrared Applications

Altera Using FPGAs to Render Graphics and Drive LCD Interfaces

Altera Taray Avoiding PCB Design Mistakes in FPGA-Based Systems

Altera Simplifying Simultaneous Multimode RRH Hardware Design

Altera Generating Panoramic Views by Stitching Multiple Fisheye Images

Altera FPGAs at 40 Nm and )10 Gbps- Jitter, Signal Integrity, Power, And Process-Optimized Transceivers

Altera Enabling Ethernet-Over-NG-SONET_SDH_PDH Solutions for MSPP Linecards

Altera Automating DSP Simulation and Implementation of Military Sensor Systems

Altera Assessing FPGA DSP Benchmarks at 40 nm

Altera Using Zero-Power CPLDs to Substantially Lower Power Consumption in Portable Applications

Altera Understanding Metastability in FPGAs

Altera Six Ways to Replace a Microcontroller With a CPLD

Altera Reduce Total System Cost in Portable Applications Using MAX II CPLDs

Altera Protecting the FPGA Design From Common Threats

Altera Implementing a Cost-Effective Human-Machine Interface for Home Appliances

Altera FPGA Coprocessing Evolution- Sustained Performance Approaches Peak Performance

Altera Energy-Aware Appliance Platform- A New Approach to Home Energy Control

Altera Enabling Design Separation for High-Reliability and Information-Assurance Systems

Altera Using Zero-Power CPLDs to Substantially Lower Power Consumption in Portable Applications

Altera Understanding Metastability in FPGAs

Altera Six Ways to Replace a Microcontroller With a CPLD

Altera Protecting the FPGA Design From Common Threats

Altera Implementing a Cost-Effective Human-Machine Interface for Home Appliances

Altera FPGA Coprocessing Evolution- Sustained Performance Approaches Peak Performance

Altera Energy-Aware Appliance Platform- A New Approach to Home Energy Control

Altera Enabling Design Separation for High-Reliability and Information-Assurance Systems

Altera Reduce Total System Cost in Portable Applications Using MAX II CPLDs

Altera Using LEDs as Light-Level Sensors and Emitters

Altera Taking Advantage of Advances in FPGA Floating-Point IP Cores

Altera MAX Series Configuration Controller Using Flash Memory

Altera Leveraging Cost-Optimized FPGAs to Deliver OTN Mapper Solutions

Altera High-Definition Video Deinterlacing Using FPGAs

Altera Design Security in Stratix III Devices

Altera Decrease Total System Costs With Industry's Lowest Cost, Lowest Power FPGAs

Altera Adding Hardware Accelerators to Reduce Power in Embedded Systems

Altera Supporting Digital Television Trends With Next-Generation FPGAs