CONTENTS Ly SAFETY. cess eee Aa. 1.2. 1.3. Lede 13. 2, GENERAL INFORMATION.++4« Bale 2.2. 2.36 3, CIRCUIT DESCRIPTIONS....2+6 Bele Safety preeautions. Caution and warning statenents. Symbolss...ee. Inpaired safety protection. General clauses.. Introductions ..++ Gharacteristics.+++ Cathode ray tube. Operation modes +3. vertical. 4, Horizontal, +5. Triggering.. 16. Menory. :7, Display 28. 2 a “a External clock + Caltbration output. O.outpues 1.Power eupply Environmental characteristics Blockdiagram description... 3.11. Vertical channel... 3.1.2. Horizonta? channel, 3,1,3, Wieroprocessor control system... 3.1.4, Timing... 3.145. C.R-T. display section 3.1.6. Power supply. Description of the vertical sections... Input couplings. Input atteneatorescee. Impedance ccnverter 3.2.4, Pre-amplifier. 3.2.5. Trigger pick-of: 3.2.6. Normal invert switch..s.seee 32.7. 3.2.8 Position coatrole-sesees on page aed del el Bt 313 24 315 HIS 3-15 315 3416 316 3416 3-16 3417 00%02 + C and D channels. O.Digitel channel switch. 2iconposite erigger pick-off. 3.Digital storage circuits, 4 Final Yoamplifier.sesseeee #5 e 2 a é 5B & 33 Triggeringssresserseeee seseeeeseees SOR 3.3.1. Trigger source selection and preamplifiet...ses, 3-21 3.3.2. Impedance converterssersessesssseeseeueee + 32 3.3.3, Trigger comparator ssseseverecesreeesaeees et 313.4, Peak to peak level detectoresesee + RL 3.3.5. TeV. synchronisation separators... + 322 3.4 Time-base generator. seeeeee 3e2h 3.4.1. Sweep generatorsseerees feeeeenee Be2h 314.2. Hold-off circultesseees ase + 325 3.4.3. Sweep gating logic.. seeees 3825 3.4.6, Auto sweep cirevites. deseeeeees 3027 3.4.5. Final X amplifier... + a7 35. Cathode-ray tube circuit. + 3429 3.5.1. C.R.T. controls. + 3429 3.5.2. geamplifier sss. + 3-29 3.5.3. Calibrator.. + 3-32 3.6. Power supply - 3633 General seen 3033 Mains transformers. fees 3033 Converter and stabilized power supply. +3633 Thlunination circuitessseee +3635 seaeeeseoesaneenneees + 3635 Digital storage clreuits.... seetseeseeeees 9936 General eseeceececnerersoeeees + 3036 Microprocessor control circuit. + 336 Adaption citcuttessrereeee ers Min/max cireuft... +3645 Input/display circult.. + 3-48 Control Logicesseeees + 3-65 ADC Logicvssseseeeees + BTS Adaption CIrCUite essere + 385 TEEE-488 optionesss+ fetes 3688 4, DISMANTLING THE INSTRUMENT. s++eeeeeees + aed fale General informations sseessereee fol teveeeeeees Gel 42. Ronoving the instrument covers. 43. Access to parts for checking and adjusting procedures.PERFORMANCE CHECK... Sale 5.26 543. 5.4. CHECKING AND ADJUSTING. ele 6.2, 6.3. bade 6.5. 6.6. 6.76 General Informations .ssreeeeeeseee Preliminary settings... Recommended test equipment.. Checking procedure General information. Survey of adjusting elements and euxiliary equipment. Interaction tablessssereseeeees Power supply ad justings 64ele Mains currents .seeee 6.4.2. Supply voltages. Cathode-ray-tube circuit ad juatings. Ge5ele Intensityeeseeee 6.542. Trace rotation.. 6.56 6.56 Adjusting and checking of the analog oscillo~ seape partes 1. Yamplifier balance.. 2. Trigger balancess.seseeseesenee 3. Time coefficients and sweep linearity..seeeeeeee 4. Vertical ampliflerssssseeeees 5. Triggering.. 6. a Be X deflection, Calibration voltagessessesseeseveseeuneeceaeeeee Mains voltage variation, Adjusting and checking the digital oseillo~ scope parts. G.7eL. Adjusting X- and Y- adaption anplifiers...e.s.s 6.7.2, Adjusting of the sequential sampling circuit 6.7.3, Time-base check.. 6.7.4, Vertical balance and sensitivity. 6.7.5. 6.7.6. 6.7.7. Equality between memory on and off. Adjusting of the MIN/MAX circulte.s. Adjusting of the ¢ and C channels... 03 6-2 6-5 6-10 6-10 6-10 el el el bell 6-11 6-12 6-12 6-13 61h 6-15 o18 6-21 6-26 6-26 6-27 6-27 6-27 6-28 6-30 6-30 6-31 6-32oa 7. CORRECTIVE MAINTENANCE. seteeeeeeeeeereee Fol Fale Replacenents. Tedel, Standard partsveeeeeeee 7.1.2. Special parts. 711.31 Transistors and Integrated circuits T.l.h, Static sensitive components 7.1.5. Handling MOS devices... {Removing printed circuit boards, + Replacing knobs, textplate and front unites... Replacing Internal fuses.. Replacing the C.R,Tes G.Renoving cabinet plates. Tee Soldering techniquesssseeceeeeuseeers + 7-13 7636 Trimming tool Kiteseesseeesereeseeceeeeseanenees THd3 Teds Recalibration after repaitesssseee vee T=18 15. Instroment repackingsssseeseseceeeeeeeeeeeseeses THI4 166. ‘Teouble shootings. ++. 714 7.6.14 Introductionseesssrerves : 7-14 7.6.2. Trouble shooting techmiquessserseee 714 We Service routines 7-16 7+7s1, Power-up routine... 3-16 7.7.2. Service routines 7-16 7.7.34 Description of the service routines. 7-20 7.7.4, Detailed description of measuring in 7-23 8, SAFETY INSPECTION AND TESTS AFTER REPATR AND MATNTENANCE IN THE PRIMARY CIRCUIT. .cseseeeseeseceeeeusneeeeeseeeannen Bel Bel. General directivesseeesees seeeeeeee 8.2. Safety components sssesseeseereaeeeeeee Bl 8.3. Checking the protective earth connections. a1 Bode Checking the {nsulation resistance. teens Bol 8.5. Checking the leakage currentsssssseeeeseeseeeeee G2L 8.6. Voltage testeserereseres seteeeeeeeees 82 9. PARTS LIST. cette eeeeeeeees 9-1 dale Mechanical partssseee seeeee + ob 9.2. Electrical parts.ssscseceseeeeeeecsesseaneaeenes 96 9.3. IEEE-488 dus interface unit AIM (PMB9SS)..seeeee 9-3810. P.C.B.’S AND CIRCUIT DIAGRAMS. +++4+ 11, LIST OF SIGNAL DENOMINATIONS. 12. ACCESSORIES 12.1. 12.26 13. MODIFICATION SHEETS. +444 12s1s1ad 12.1.2.Matehing the probe to your oscilloscope. 12.1,3.4d justing the h.f. step responses... 12.L.a.Dismantling the probesseseeseeeeesoeee 12.1.5.Disuantling the compensation box... 12.1.6.Replacing parts 121.7 .Parts Listeseseee 12.2.1, 1EEE-488 bus interface PHB95S. Accessories supplied with the instrunent. rl Passive probe PMB927A. Accessory information for optional items. page 10-1 usd 12} 12-1 12-1 1263 12-3 12-4 12-4 La 1265 1266 12-6 13-1 086 LIST OF FIGURES Fig. Fig. Fig. Fig. Pee Fig. Fig. Fg. Fig. Figs Fig. Fig. Fig. Fig, Fig. Figs Fig. Fig. Fig. Fig. Fig. Fig. Pig. Fig. Fig. Fig. Fig. Fig. Fig. Figs Fig. Fig. Fe. Fig. Fig. Fig. Fig. Fig. Fig. Fig. rig. ele 3.6. 3.10. ae 312. 3.13. Bulb 3.156 3616, 3al7e 3.8. 3.19, 3.20, 3e2Le 3.22. 3.23. 3.24. 3,25, 3.26. 3.27, 3.28, 3.29, 3.30. 3.3Le 3.32. 3.33. 3.34, 3.35. 3.36. 3.37. 3.38. 3.39. 3.40. 35 MHz Digital storage oscilloscope PH 3305. Detailed blockdiagram I.. Detailed bleckéiagram IT. Complete display of all the values of one channels eeeeseeeeeee Simplified diagram of the analog channel switch... Signal on the base of transistor T1013. Avertical interval with frane synchronisation PULSE BFOUPseseececeseaceeeueeaeseeenere ‘Mine relation diagram of the sweep-gating logic in the AC or DG modes.++4 Shunt feed-back amplifier Complete display of atl the values of one chaanelsss. Basic diagram of the converter. Min/ams timing disgren + peak detectorssss+s++ TSH gate. Trigger position on C.k.T. displays. Variable length of the pre-trigger nenory/ counter Pre-triggering. WRITE COUNTER in SAMPLING=I modes seseseeeeeeee WRITE COUNTER in SAMPLING-IT mode.. Loading of the WRITE COUNTER. Display timing. Display without display quart selection.. Display with display quart selectionsyysseeeee Control counter timing diagram... Deglitching of the XDAC......4- Chopper signals in four channel aode, Chopper circuit. sssssseeeeesees Chopper signals Chopper circuit Chopper signals Chopper cireutt Chopper circuit Chopper signals.. Chopper circuit. Chopper signais.. Display tining I. Display timing Il.seseeeseeeee Maing of signal CTBseeeeeeeeeeeeeeeeeeee La-bit count length register... WRITE COUNTER in SAMPLING I node. SAMPLING I mode principle Bast rampeseesses page 3-3 39 Bele 317 3-22Fig. Pig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fige Fig. Fig. Fig. Pig. Fig. vig. Fig. Fig. Fig. Pigs vig. Fig. Tig. Fig. Fig. Fig. Fig. vig. Figs Fig. Fig. Fig. Fig. Fig. Fle. Figs Fig. Fig. 3.41. 3.426 3.43. 3.44. 3.5 3.46. 3.47. 3.48. 3.49. 3.50. 3.51. 3.52. 3.53. 35k. 3.55. page Comparatorsessseeeeee ve + 79 WRITE COUNTER in SAMPLING 11 node. sees 3°80 SAMPLING [I mode principle... 3-81 Wold-Off LOgicesersaeseeeseenereee 3-81 Fold-off logic. te 3-82 Hold-off Logic.. Hold-off timing. Adjustment of correct DACSTATR level. Adjustment of start point Timing of signal RESDET, ‘Timing conversion + write cycle... Deglitching DAC.....++ Blockdlegram IRBE interface Handshake cycle. Gable + connectors..++++ Kenoving the instrument cOverasseseeeeeseeeeee dol Adjusting and checking the power supply..+e++- 610 Adjusting elements amplifier board AS.eseseee. 68 Adjusting elenents attenuator board A3...+.4.- 6°13 Adjusting the square wave responsesssseeeesees 6717 Adjusting elements logic unit Allecccseccsteee 6924 Adjusting elonants adaption unit A¥.eseseereee 6624 Adjusting elenents MIN/MAX unit Al0vrecseeeeee 6°24 Adjusting elements AUX, channel unit Al2...... 6-24 Removing printed circuit boards... Removing printed circuit boards. Removing the knobs. te Removing the froat unitesseeee++ Removing the Front unityessseess Renoving the front unit...ssee.- cad Replacing a switch of a pushbutton unit. 7-9 Replacement of the thermal fuse....+. + 10 Renoving the carrying handlesssseeeeseeeeseees Z12 Removing the bezel and the contrast plate...., 7n12 Trimning tool kitesers Front view showing item cumbers. Rear view showing itom numbers.. 9-4 Handle iten nuabers . 9-5, Knobs teste : 9-5 AC power unit (Al) seesesseeeeeseeee = 10-4 DC power unit (A2)s..eee tees ee eeeeeee © 10-5 Front unit (A3)+ seeeeeeeeee 1098 Attenuator unit (A301). seers 1009 Attenuator unit (A301)......5 + 10-9 0708 Fig. Figs Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Figs Fig. Fig. Fig. Fig. Pig. Fig. Fige Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Figs Fig. 10.5, 10.7. 10.8. 10.9. 10.10. 10.11. 10.126 10.13. 10.14. 10.15. 10,16. 10.17. 10.18. 10.19. 10.20, 10.21. 10.22. 10.23. 10.24, 10.25. 10.26. 10.27. 10.28, 10.29. 10,30. 10.31, 10.32. 10.33, 10.34, 10.35, 10.36. 10.37. 12d. 12.2. 12.3. 12.4, 12.5. 12.6. 12.7. 12.8, 12,9. 12.104 12.1. Attenuator switch (4302) Time-base switch (A303) +++ Memory switch unit (A304) «see. Ledbar unit (4305)...... Snooth switch unit (A306)..+eeeee Triple led unit (A307). amplifier unit (A5) with components and upper side tracks... Amplifier uait (A5) without components and rear side tracks Intens unit (46) Delay Line unit (A7).... SV De untt (8). Adaption unit (A9) se. Min/max undt (ALO) sessee Logic unit (All) sssseesesssserseeseeeeeees Ta tundt (ALOR) seeeeeescerenee Auxiliary channel unit (A12) see ERT untt (A13).. TREE-488/TEC-625 bus interface option (Al4). DIAGRAM 1 Vertical channels (A5) DIAGRAM 2 Channels C and D (AL2) DIAGRAM 3 Digital channel switch (49) DIAGRAM 445 Horizontal channels (A5). DIAGRAM 6 — Cathode-ray tube circuit (A5)... 7 8 DIAGRAM 7 Power supply (Al) «++ DIAGRAM 6 uP control cireult (AL1) DIAGRAM $ — Adaption circutt (A9).« DIAGRAN 10 Minfmax circuit (A10).. DIAGRAM 11 Input/display circuit (All) DIAGRAM 12 Control logic (ALL). DIAGRAM 13 ADC logte (Al1).. DIAGRAM 14 Adaption circuit (A9).++ DIAGRAM 15 TEEE-488/IEC-625 option (Al Imput impedance vs frequency. « components (peak) of maxinum rate: voltage vs frequency... Usefull bandwidth vs frequency. Under-compensation..+ Correct~compensation. input Over-compensation. Preset potentioneters correctly adjusted....., Rounding dye to incorrectly adjusted potentio~ Meterseeeeses Overshoot due to incorrectly adjusted poten= tiometerseeeeeeeee Dismantling and accessories. Printed witing board showing adjusting elenents, circuit diagran. pepe 10-10 10-19 wr. 10-11 10-12 10-12 10-14 1o-is 10-17 10-17 10-18 19-19 10-19 10-21 10-21 10-21 10-21, 0-24 10-27 L034 10-35 10-40 10-61 10-43 10-48 10-49 10-51 10-56 10-57 10-59 10-62 10-63 1261 12-2 12-2 12-3 12-3 12-3 12-3 12-3 12-3 124 12-61.2. 13. 14, wt SAFETY INSTRUCTIONS Read these pages carefully before installation and use of the instrument. ‘The following clauses contatn inforsation, cautions and warnings which aust be followed to ensure safe operation and to retain the instrument in a safe condition, 4djustuent, maintenance and repair of the instrument shall be carried out only by qualified personnel. SAFETY PRECAUTIONS For the correct and safe use of thie instrument it is essential that doth operating and servicing personnel follow generally-accepted safety procedures (n addition to the safety precautions specified in this manual. Specific warning and caution statements, where they apply, will be found throughout the manual. Where necessary, the warning end caution statements and/or symbols are marked on the apparatus. CAUTION AND WARNING STATEMENTS CAUTION: ts used to indicate correct operating or maintenance procedures in order to prevent damage to or destruction of the equipment or other property. WARNING: calls attention to a potential danger that requires correct procedures or practices in order to prevent personel injury. SYMBOLS High voltage > 1000 ¥ (rea) LN Live part (blacie/ yellow) Read the operating (black/yellow) instructions. Protective earth (black) (grounding) terminal IMPAIRED SAFETY-PROTECTION Whenever it is likely that safety-protection has been impaired, the instrument must be made inoperative and be secured against any unintended operation. The matter shold then be referred to qualified technicians. Safety protection is likely to be impaired if, for exemple, the instrument fails to perform the Intended measurements or shows visible danage.12 1.3. Sede 1.5.2. 1.5.3. Ledahe 15.5. 1.5.65 GENERAL CLAUSES WARNTN ‘The opening of covers or removal of parts, except those to which accesa can be gained by hand, is likely to expose live parts and accesible terminals which can be dangerous to Live. ‘The instrument shall be diconnected from all voltage sources before it is opened, Bear in mind that capacitors inside the instrument can hold their charge even if the instrument has been separated from all voltage WARNING: Any ioterruption of the protective earth conductor inside or outside the instrument, or disconnection of the protective earch terminal, is likely to make the instrument dangerous. Intentional interruption ig prohibited. Coxponents which ere important for the safety of the instrument may only be renewed by components obtained through your local Philips organisation. (See elso section 8) + After repair and maintenance in the primary circuit, safety inspection and tests, as mentioned in Section 8 have to be performed,Qele 2 GENERAL INFORMATION INTRODUCTION ‘The PM 3305 Digital Storage oscilloscope is a compact instrument, featuring ergonomic design and extensive measurement capabilities. A large 8x10 screen, with internal graticule lines, provides easier viewing and an 10 kV accelerating potential gives a high intensity trace with a well-defined spot. As a real time oscilloscope the PM 3305 is characterised by the following features: ~ 2av/div sensitivity at 35 Re. - A wide choice of display modes, including the an ADD facility. ~ X/¥ display. - TY triggering. As a digital storage oscilloscope the versatile circuit arrangement, combined with the software for the microprocessor offers a wide range of facilities, including: = Brilliant display. = Excellent resolution because of 4K x 8 bits memory to be éisplayed on one full screen. = 4k bytes pre-trigger view (one screen). = COMPARE mode. = MIN/MAX mode. 4 Channels. ~ Max. 8 signals on the screen in COMPARE mode. = 2 Miz AD conversfon rate (maximum). ~ IBEB-488 interface option, ‘The instrument operates on an a.c. mains voltage of 100 V, 120 ¥, 2200 or 240Y, In addition, field applications for the oscilloscope are facilitated by external battery operation. Marie PIG. 2.1, 35 Miz Digital storage oscilloscope PM 330522 2ide G. 22d 262.26 ‘CHARACTERISTICS i Performance Characteristics “Properties expressed in numerical values with stated tolerance are guaranteed by N.Y. Philips’ Gloeilampenfabrieken. Specified non= tolerance mumetical values indicate those that could be nominally expected from the mean of e range of identical instruments, ~This specification is valid after the instrunent has warned up for 30 minutes (reference temperature 23°C). Safety Charactertstics This apparatus has been designed and tested in accordance with safety Class I requirements of IEC Publication 148, Safety Requirements for Electronic Measuring Apparatus, UL 1244 and’CSA 5563, and has been supplied in a safe condition. Initial Characteristics ~Overall dineasions: sReight (excluding feet): 137 am. sWiéth (excluding handle): 337 nm. «Depth (excluding controls) : 452 mm. “Maximum Weight (Yass) Pl kg. ~Operation position a) horizontally on bottom feet b) vertically on rear feet c) any angle between a) and b) Cathode ray tube: type D1g-125 GH/ 117 “Total accelerating voltage 10 ky “Screen 8x10 om, metal-backed (1 div. equals 1 em) -Phosphor type P31 (GH). Optional P7 (GM). ~craticule internal, , Graticute L1luni~ nation continuously variable “Trace rotation —screwiriver adjusted MEMORY OFF MEMORY ON Operation node ‘Memory off only analog part in operation Memory on Digital storage part in operation SINGLE not de~ pressed on cach trigger, nenory contents are overwritten Not triggered is indicated by the LD NOT TRIG’D SINGLE depressed| After "RESET" menory con- tents are overwritten on first trigger pulse recei- ved. Armed status is indicated by the Lep "wor TRIG’D"2.2.3. ~pirect/sempling tical: “Number of channels ~Channel display/ acquisition modes “Polarity inversion Chopping Frequency “Display time per channel Acquisition Compare -Min/Yax ~Dynanic range “channel A and B ~channel € and D MENORY OFF 2 channels (A and 3) A only 48 oniy Zand #8 alternated JA and =B added A and $B chopped Channel B can be inver- ted = 500 kuz = 600 ns 2h divisions for fre~ Jquencies < 10 MHz 28 MEMORY ON with time-base setting, sampling mode or direct ode is selected autonati- cally dependiag on sweep speed. For time-base 100,us/div. £0 0,lus/div. the “pep ONLY" LED indicates that sequential sampling is selected. 2 channels (A and 8) and 2 auxiliary channels (C aad D) A only +B only A and +B added A and +B chopped Pushing ALT or CHO? gives chop node, except with MIN/MAX pushed. This gives alternate mode for A and B A, 4B, C and D chopped ASB (ASX, Y=B) Channel Bean be iaver- ted Depends on sampling frequency 50 % of memory capacity is @teptayed continuously (each second dot on screen) ‘The other memory places are displayed and continuously refreshed. Fach time that the OOMPARE button is released and pressed again, the compare uenory is filled with the latest informacion fn the active memory. When button is depressed 2 peak detectors are operati- ve. Maximum peaks ate sto- red on each second clock- pulse. Minimun peaks on the other clock pulses. Works for channel A, +3 or A and +B alternated. 24 divistone for fre~ quencies < 10 Mitz 10 divisions24 Bandwidth channel A and 3 (Dey channel A and B (ac) -in Min/Mex res~ pectively “channel ¢ and D -Riset ime channel A and B win Min/ Mex channel ¢ ané D “Pulse aberrations ~channel A and B (testpulse 6 div| risetine 1 ns) “channel ¢ and D (tesrpulse 6 div] risetine 1 ns) Deflection coeffi- cients “channe? A and B -channel ¢ and D Continuous control (non calibrated) channel A and B Vertical position~ dag “channel A and B channel ¢ and D “Input impedance channel A and channel C and D Input coupling channel A and B channel ¢ and D Maximum raced input voltage “channel A and B “Maximum rated input voltage schannel ¢ and D Deflection accurs- ey channel A and B channel C and D ~CMRR “In AcB mode af ter adjusinent at DC. channel € and D MEMORY OFF DC - 35 Mie 2He - 35 WRe < 10 ns z iss < £ 3% (peak-peak 2,3 > + 8 divisions IMohm // 20pF AC-0-DC 400v (de + ac peak) below 100 kHz 42V (de + ac peak) below 100 kHz 43% > 40 dB at 1 Maz MEMORY ON DC - 35 MHz (-3 dB) 22 - 35 bie (-3 dB) DC = 30 Miz (-3 dB) 2Hz - 30 MRz (-3 GB) DC - 1 Mie (-3 dg) < 10 ns < 11,6 ns < 350 os < + 4% (peakepeak, < 5a) cm 2m - 10V per diviston 1-2-5 sequence O,1W/éiv (rear BNC) 1,0V/div (rear BNC) 12> 2,5 + 8 divisions ¥ 95 divisions IMobm // 20 pF 10 Kohm + 3% ac-0-De DC 400V (de + ac peak) below 100 kHe 42¥ (de + ac peak) below 100 kHx leit > 40 dB at i mae > 50 €B at 50 KHe2e2ahe Rated common mode voltage “channel @ and D at 0,1 v/div at 1,0 v/diy 20aV/aiv continuous con trol -normal/invert channel B ~aenory ON/OFF ~temperature drift at 23°C “Crosstalk beeween channels “Linearity error reference IEC 351 Bort zon: =Tie—base ~time coeffi~ cients ~continuous con- trol ~magnifier -positioning coefficient acx curacy ox ~additional magnifier x 10 sresolution single trace dual trace four trace -aexinum coaver- sion frequency cvistble signal delay MEMORY OFF < 0,3 div/hour > -40 @B at 10 MHz > -30 dB at 35 Mae 2,5 Cuncal) x 10 calibrated > #5 divisions <4 9% < + 2% (Ftrst div. eieluded) > 1,5 divisions at 10 as/div 28 MEMORY OW < + 200 see aaximur rated input voltage < 0,1 atv <1 div < 0,5 div <1 div < 0,3 div < 0,3 div/hour 40 dB at 10 Hae 30 dB at 35 Miz x 0,5 8/div to 0,1 jus/div and 5 s/div to 1 S/div when TIME/DIV is depressed 1-2-5 sequence 1 +> 2,5 (uneal) works only for the time- base settings 100/us/div to 0, jus/aiv. x 10 calibrated > 4 3 divisions <4 3% <4 2% (First div. excluded) 400 samples/div. 200 sanples/div, 100 sauples/div. in COMPARE respectively 200 samples/div. 100 sanples/div. 50 samples/div. 2 Mie > 2 divisions at 10 ns/div.26 -trace junp 0 ,2us/div. O,1pus/aiv “X-Deflection ~deflection coefficients channel A or B ~BxXT TEXT + 10 LINE, ~bandwiden, De ac 8 div De to 1 MHz 5 Hz to 1 Mile < 3° at 100 kHz 24 divisions up to 100 kHz < + 10% channel A, channel B external external : 10, Line and’ composite AUTO (free-run in ab= sence of trigger after 100 as; see also level range) AC coupled DG coupled TW (IV line or frane switehed by TIME/DIV rotary switch). TV Line #< 20/us/div Tv frame:> 50/us/dtv 20 Hz - 50 Mie 5 ue ~ 50 Mae 0 = 50 Mie < 1/2 div at 5 Mite < 1 div at 35 Miz < 0,2 (2) Vp at 35 Mite 0,1 (1) vpp ac 5 MHz < 0,7 div syne. pulse amplitude < 0,15 (1,5) ¥ syne pulse amplitude MEMORY OW < 0,3 div (in x 1) increasing to < 0,8 div Gin x 1) channel A, channel B external ,external : 10, Line. (Ko composite) AUTO (free-run in ab- sence of trigger after 100 as; see also level range) AC coupled DC coupled TV (TY line or frane switched by TIME/DIY rotary switch). TV Line :< 20/us/div TY Frame:> 50/us/div 20 He ~ 50 Miz 5 Hz - 50 MHz 0 ~ 50 Miz < 1/2 div at 5 Miz < 1 div at 35 Mie < 0,2 (2) Vpp_at 35 mie < 051 Wop at 5 MRz < 0,7 div sync pulse amplitude < 0,15 (1,5) V syne pulse amplitude2.2.6, 2D trigger level range =A0TO internal ~external cexternal : 10 trigger siope ~tor- dual wexternal trigger input impedance maximum rated input voltage pte trigger Memory: number of memories| -resolution hori- zontal, “resolution verti~ cal ~menory nodes CLEAR Lock Display: “nenory horizontal expand ~channel B vereus channel & mode waccuracy ~phase difference MEMORY OFF proportional to peak peak value of trigger signal > +6 div > > pos/neg-going 1 Mohm // 20 pr 4000 (ae + ac peak) below 100 Kkz. a7 MEMORY on propertional to peak~ peak value of trigger signal, > + 6 div > Fog y > sels 18 By pos/neg-going works from 5s to 0,2ms/div erigger occurs when stgnal goes out of a fixed window of > + 0,5 div; window can be shifted by LEVEL 1 Mohm // 20 pe 400V (de + ac peak) below 100 kkiz. trigger polat can be set on beginning, 1/4, 1/2, 3/4 and end of screens 1 1 + 4096 (ax) 1: 256 (8 bits) first push clears the memory, trace in middle of screen; second push (within = 1 second) blanks the trace menory input is blocked covers 10 em screen height ax 7 overlapping nenory quar— ters can be selected (with X*MAGN 40 x ) eA TOR roared distance between signal derived from A and signal derived from B 1s 1/400 div.; the mean of two ad- jacent B values is dis— Played versus one A value28 ~position ~saooth 2.2.8. External clock: fnpur levels CETL) rn TH ~frequency switching to ex-| ternal clock ~naximum rated input. voltage a 2429+ Calibration output: output voltage waccuracy ~frequency 2.2.10, Outputs: abe OUT (rear of the in strument) wrated output levels (TTL) optionally instru-| ment bus IEEE-488 {reer of the in- strument) ~TEEB-488 -nenory dump (listen only/ telk only) MEMORY OFF MEMORY ON 0 of stored A signal will be at centre of screen Switches RC-filter in dis~ play channel with time coastant of 7 jus. freq > 40 Hz automatic freq < 40 Hz by internal switeh + and -10 V 1,2 Vpp square-wave So fare we | . Gum | Sige —_fapea] eens -— faxsre oe ' = AUSUARY CHANNEL UT 41 ATTENUNTOR UTA _ AMPLIFIER] UNIT AS. su: POWER SUPPLY UNIT At Hig, 3.1, Detailed blockdiagran T.pone | [rere ial = Ce &Belele 39 CIRCUIT DESCRIPTIONS In chapter 3.1. the block diagram is described and in the chapters 3.2, and further the detaited circuit information is described. BLOCK DIAGRAM DESCRIPTION (FIG. 3.1 and PIG. 3.2) This chapter serves to explain the main functions of the oscilloscope. This tnstrument can be used as a normal anelog real-tine oscilloscope (pushbutton MEMORY ON released) and as a digital storage oacilloscope (pushbutton MEMORY ON depressed). With this pushbutton MEMORY ON a selection can be made between an analog and a digital signal path. At che same time a selection is done between an analog time-base circuitry and a digital tine-base circuitry. Vertical channel. ‘The vertical channele A and B for the signais to be displayed are identical except for the invert facility included ia the B chaanel amplifier. Bach channel comprises an input coupling switch for 4C-DC-0, an input step ATTENUATOR and an IMPEDANCE CONVERTER. ‘The AMPL/DIV switch provides 41 or x10 gain control of the PRE-AMPLI~ FIER, which offers in conjunction with the step attenuator # full range of ¥ deflection coefficients in a In2-5 sequence. This stage is followed by a PRE-AMPLIFIER with trigger pick-off point. ‘The pre-amplifier also contains the continuous control of the AMPL/DIY switch and the POSITION control for vertical shift of the trace. Both channels ave applied to an electronic SWITCHING AMPLIFIER. ‘he SWITCHING AMPLIFIERS of both A and B channels are controlled by an ANALOG CHANNEL SWITCH which in turn 1s set for different display modes by operating the display mode pushbuttons A-ALT-CHOP-ADD-3. In the ALT mode, the ANALOG CHANNEL SWITCH is operated by @ pulse at the end of the MIB aweep, and offers alternate uninterrupted display of the channel A and B waveforms. In the CROP mode, the ANALOG CHANNEL SWITCH (channel multivibrator) is free-running at a fixed frequency of approxtmately 500 kz to drive the SWITCHING AMPLIFIERS alternately, which then are opened and closed successively, so that discrete parts of the signals of channel A and Bare displayed in rapid succession, giving the appearance of two con tinuous traces. In the ADD mode, both SWETCHING AMPLIFIERS couple the signals through, thus eéding channels A and B. By inverting the B channel (PULL TO INVERT 3) the A-B mode is obtained. In MEMORY ON mode two more channels C and D can be added to the system, selected by the ABCD CHOP pushbutton, resulting in a total of four channels A,B,C and D.310 Both channels C and D are identical, each comprising two separate in- put BNG’s, mounted at the rear of the instrument, with a fixed deflection coefficient of 0,1V/DIV and 1V/DIV. Furthermore an IMPEDANCE CONVERTER and an AMPLIFIER with a screwdriver POSITION control (to be operated on the instruments leftside). Each AMPLIFIER is followed by 2 SWITCHING AMPLIFIER which is controlled by « DIGITAL FOUR CHANEL SWITCR under the control of the microprocessor system. ‘The ANALOG CHANNEL SWITCH is blocked in MEMORY ON node and its function is taken over by a DIGITAL FOUR CHANNEL switch which is controlled by the switches A-ALI-CHOP-ADD~B and ABCD CROP via the microprocessor system. In that case all four SWITCHING AMPLIFIERS of the channels 4,B,C and D are controlled by the DIGITAL FOUR CHANNEL switch. The resulting output signals of the four SWITCHING AMPLIPIERS are supplied via the DSLAY LINE DRIVER and DBLAY LINZ to the Digital storage circuits, (See blockdiagram II FIG. 3.2). Depending on the selection of MEMORY OFF or MEMORY ON the signal is applied via the so-called "analog signal path" or the so-called “digital signal path". Selection of the analog signal path means that the DELAY LINE output As directly coupled to the input of the ¥ FINAL AMPLIFIER. Selection of the digital signal path means that the DELAY LINE output 4s coupled to the ADAPTION circuit and then to the MIN/MAX unit. With MIN/MAX selected the DELAY LINE is coupled to the MIN/MAK detectors in the "digital signal path", This circuit, which can be awitched off via the microprocessor system by operating pushbutton MEN/MAX, determines the minimum and max{mun amplitude of the analog input signal. These MIN and MAX values are applied to a MIN/MAX multiplexer. he resulting analog signal is digitized in an Analog to Digital, Converter (ADC) under the control of the ADC logic and the wicropro— cessor system. ‘The timing of the conversion 1s determined by one of the 3 following - In positions 0.5s/div. s+. 0.2ms/div of the TIME/DIV switch (DIRECT- node) by the digital time-base generator. — In positions 100,us/div. « 0,1 yus/div. of the TIME/DIV switch (sequential SAMPLING-mode) by the analog time~base generator saw tooth signal and the trigger signal. (See digital storage circuits section 3.7.7. ADC logic). In (EXTERNAL~node) by a frequency applied to the EXT. CLOGR input. After digitizing by the ADC the information is shifted vie @ TRI-STATE BUFFER through a PRE-TRIGGER MEMORY. The ADC output information 1s also applied to an ADC OUT connectot on the rear panel, This PRE TRIGGER MEMORY which consists of a RAM MEMORY, a PRE TRIGGER COUNTER and @ LATCH is configurated as a shift register with a variable length. The LATCH can be seen as the output of this shift register system. The length of this shiftregister can be varied by presetting the PRE-TRIGGER COUNTER via the microprocessor systez and depends on the operator’s PRE-TRICGER selection with pushbuttons PRE-TRIG and OFF. Furthermore the PRE TRIGGER MEMORY is controlled by the MEMORY WRITE roate.3.1.2. sat On receipt of a trigger pulse a coupling is realized between the PRECTRIGGER shift regieter output (LATCH output) and a DISPLAY MEMORY of 4096 x Sbits. Starting at the moment of triggering the DISPLAY MENORY will be completely filieg with infornation which is shifted through the PRE~ TRIGGER shift register system. The information, which was stored already in the PRE-TRIGGER MEMORY at. the moment of triggering is shown on the C.ReT. display as PRE~TRIGCER information. The contents in the DISPLAY MEMORY is influenced by the selected acquisition modes MIN/MAX, COMPARE, ABCD CHOP, A, B, ALT, CHOP, ADD and/or B, ‘Two address counters “WRITE COUNTER" and "DISPLAY COUNTER" can be connected to the DISPLAY MEMORY address lines via a MULTIPLEXER. ‘The WRITE COUNTER is addressing to the DISPLAY MEMORY when new information has to be written In the memory and the DISPLAY COUNTER is addressing to the DISPLAY MEMORY vhen memory contents has to be dis~ played on the C.R.T, screen, Tt is also possible to write or read information to or from the DISPLAY MEMORY by a controller via au IEEE-688 option. This is done via a TRI-STATE BUFFER. ‘The contents of the DISPLAY MEMORY can be visualized on the C.R-T. screen under the control of the DISPLAY COUNTER and the wicroprocessor system. Different display modes can be selected by operating one or more of the pushbuttons X-A/Y=B, SMOOTH, DISPLAY QUART. Tae digital output information of the DISPLAY MEMORY is applied via an AVSB AND QUARTER LOGIC to a vertical Digital to Analog converter (Y- Dac). The resulting analog signal information is then applied via a SMOOTH filter and ADAPTION circuit to the vertical PINAL ¥ AMPLIPIER which directly drives che vertical (¥} plates of the C.R.T. Horizontal channel Trigger signals can be derivad from the A and B channels, from the natns supply or externally fron the EXT-input and are selected by che teigger- source switch A= B- EXT ~ EXT#10 ~ COMP - LINE, With the A and B pushbuttons both depressed, composite triggering is derived from the DELAY LINE DRIVER. (Composite triggering is not possible when the oscilloscope is used ag digital storage oscilloscope). The trigger coupling switch provides the facility of AUTO, AC, DC or TV triggering. The polarity of the trigger signal, negative or positive-going, on which the display will start is determined by the +/- SLOPE control, which changes the output polarity of the TRIGGER COMPARATOR. With the AUTO switch depressed, the peak-to-peak level of the signal then determines the range of the LEVEL control. With AC or DC selected, the range of the LEVEL control is fixed. Selection of DUAL enables the display to be triggered on either the positive-going or the negative-going edge of the input signal. For normal time-bage operation (MEMORY ON released) the PINAT, X- AMPLIFIER is fed by sweeps from the TIME-BASE circuit.312 Bebe When AUTO is selected, in the absence of trigger signals, the time~ base generator output is directly fed back via the HOLD-OFF CIRCUIT and gate to its input. This causes the sweep to free-run and a trace is always visible. The AUTO mode can be used in all instances where the TRIG mode 1s va~ lid, except for signals below 20 Hz or pulse trains with an off period exceeding 100 as. As soon as trigger pulses are available, the free-running state of the time~base generator is automatically terminated and noral triggering is resumed. When either DC or AC is selected, AUTO is inoperative. Sweeps are then only produced when a trigger signal is present and the LEVEL control is set correctly. ‘The HOLD-OFF CIRCUIT, as its nane implies, ‘holds off’ trigger pulses from the tine-base input until the flyback trace has completely retur- ned and the tine~base circuits are completely reset, The TIME/DIV switch positions control the specd of the time-base sweep in a 1-2-5 sequence together with the uncalibrated continuous control. Setting the TIME/DIV switch in the X DEFLECTION position inhibits the time-base output of the PINAL, X AMPLIFIER and permits horizontal deflection from another source. Worizontal shift of the time-base line is achieved with the X POSITION control and it can be magnified by a factor of 10 using the X MAGN push-pull witch. The FINAL X-AMPLIFIER drives the horizontal (X) plates of the CRT. With MEMORY ON selected the addresses for the DISPLAY MEMORY are converted to an analog staircase signal by the microprocessor con— trolled X DAC and then applied to the FINAL X-AMPLIFTER via a SMOOTH filter and ADAPTION circuit, In X+A/Y=B mode the AVSB and QUARTER logic applies the signal value of channel A to the X DAC and the mean value of 2 adjacent channel 3 values to the ¥ DAC, This is controlled by the DISPLAY MEMORY COUNTER. Now the channel A signal is displayed horizontally and the channel 5 signal ts displayed vertically. QUARTER display is realized by the AVSB and QUARTER logic under the control of the microprocessor system. Micro~processor control system ‘The microprocessor control system consists of a micro-processor, ROM and RAM menories, latches, input and output porte, address decoder and relevant logic circuits. The following functions ate under its control: “Reading of switch settings used fn MEMORY ON mode. -Reading of the TIMB/DIV switch settings. ~Reading of the display mode pushbuttons. ~Control of pilot lanps for DISPLAY QUART and PRE-TRIG. =Control of pilot lamps RENOTR, REP ONLY and NOT TRIG’D. “Control of the C.R.T. display.Belede 3.15. 13 Furthermore the microprocessor systen controls several sections in the oscilloscope. In addition to these oscilloscope functions, the micro-processor control system also supervises the handling of the IEZE~488 Bus- interface option, Timing Time-base frequencies aud control and timing signals are generated by the PHASE LOCKED LOOP, CONTROL COUNTER, CONTROL LOGIC and CHOPPER roclc. GRT display section. In MEMORY OFF the Z-auplifier is controlled by timing signals derived from the horizontal time-base channels to provide trace blanking of the C.R.T. during the flyback and hold-off time, In addition, controlled by the vertical logic, it blanks che sweep du ting switching transients in CHOP mode, The 1.f. components of the blanking signal are modulated and demodula~ ted (for voltage isolation purposes) before they are applied together with the a.c. - coupled h.f. voltage components to che Wehaelt cylinder. In MEMORY ON the way in which the contents of the DISPLAY MEMORY is displayed on the C.R.T. screen depends on the functions which are selected by the operator. ‘Tae contents of the DISPLAY MEMORY are 4096 words, each consisting of ® bits, Each G-bit word is capable of indicating 256 different anpli- tudes (t.e. 2° = 256) : ¥ values. Each address of the menory corresponds to a by the selected function specified vertical line of the display along the X-axis. ‘The 4000 words of the DISPLAY MEMORY contents of 4096 words are dis played in a display area of more than 8 vertical divisions and 10 hort zontal divisions which 1s divided into 256 x 4000 dots. (96 dots are displayed outside the 10 horizontal divisions). A jub-controlled DISPLAY COUNTER sends 4096 different addresses sequentially (starting with address 0 and ending with address 4095) to the DISPLAY MENORY and to the Digital~to—Analog-Converter (DAC) of the X-systen. Jo provide the discrete steps for the horizontal tine~base display the output of the X-DAC Is a linear statrcase voltage, which is applied to the FINAL X-AMPLIPIER. The resulting output of the FINAL X-AMPLIFIER is routed to the horizontal deflection plates of the CART Similarly, the 8-bit instantaneous values for each address (i.e. the Y- information) are converted into analog eignale by means of the Y-DAC. The converted signal is then applied to the FINAL-Y-AMPLIFIER. Trace intensity is controlled by the 2 AMPLIFIER and can be adjusted by means of the INTENS control.a4 Belebs \\ i | I (oisuay Meso | \ i { a FIG, 3.3, Complete display of all the values of one channel, ears: i ‘The FOCUS control drives the focussing electrode of the ORT to regulate the sharpness of the trace, ‘The trace should lie in parallel with the horizontal graticule Lines, if any deviation occurs, it can be corrected with the TRACE ROT potentioneter. In MEMORY ON mode (signa} STORE is active) the blanking pulse is con~ trolled by the display memory logic for the different display modes. Power supply. The power suply operates efther from a.c. mains voltages of nominally 100V, 120¥, 220 or 240V or optional from a d.c, source of 24-27 V. A switched-mode circuit employing an integrated circuit provides emoothed d.c. outputs of +180¥, -180V, +38¥, +5V, +12V, -12V, +60V,, ~60¥. A separate DC unit supplies a +5V DC voltage for the logic circuits. The EHT voltage for the accelerator anode of the C.R.T. is derived Fron a voltage quadrupler circuit taken from the converter transformer secondary circuit that supplies the ~1500 ¥ for the cathode of the G.R.Te ‘The brilliance of the graticule illumination lamps can be varied with the ILLUM control. The CAL unit provides the calibration square-wave voltage.3.24 36201 3.22. 3.2634 318 DESCRIPTION OF THE VERTICAL DEFLECTION SYSTEM (Diagram 1) The vertical channels A and B for the signals to be displayed are identical, each conpristng an input coupling switch, an input step attenuator, an impedance converter and a preanplifier with trigger pick-off. A channel mltivibrator, controlled by the display mode pushbuttons , switches either channel A or channel 3 to the final Y amplifier via the delay line driver and the delay line, The final Y amplifier feeds the ¥ deflection plates of the cathode-ray tube. The individual stages of the vertical deflection system are now described in some detail. As the signal paths for channel A and channel B are basically identical, only the channel B signal path ts described, Input coupling (unit A3) Input signals connected to the B input socket X3 can be a.c. coupled or internatly disconnected. In the AC position of S14, there is ¢ capacitor (C401) in the signal path, This capacitor prevents the D¢ component of the input signal from being applied to the amplifier. In position DC of switch $14, the input signal is coupled directly to the step attenuator. At the same time, blocking capacitor C401 is discharged via R602, to prevent damage of the circuit under test by a possible high charge. S15 (0) isolates the B input signal and earths the channel input for reference purposes; e.g. for calibration or centering the trace. Input attenuator (unit A3) The input attenuator is a frequency-compensated, high-impedance voltage divider with twelve positions. The overall attenuation of the stage is determined by the combination of the selected sections of two voltage dividers. The various combinations are selected by the twelve positions of the frontpanel AMPL/DIV attenuator switch 88. The first divider sections attenuate by factor of 1,25, 3.125 and 6.25 and the second divider sections attenuate by 2 factor of Ix, 10x and 100x. With the overall combinations of attenuation, nine different deflection coefficients are realised from 20 mV/div to 10 W/div in a 1-2-5~ sequence. Only for the most sensitive positions 2 m¥/div, 5 aW/div and 20 mV/div of AMPL/DIV attenuator switch $8, the gain of the Y amplifier 1s increased by a factor of 10. The input capacitance of the attenuator cannot be adjusted in the individual positions, Small differences of approx, i pF are allowed. Capacitor aetworks are provided in the voltage divider sections to make them frequency independent. Impedance converter (unit A5) ‘The impedance converter is formed by V604 (two matched field-effect transistors). The two FET transistors are used in source follower configuration, ‘The signal level on the gate (and on the source) of the upper FET amounts to 1,6 aV/div or 16 mV/div. Diode V601 together with che output impedance of the attenuator and also the attenuator action protects the input source follower, against excessive negative input signals. The d.c. balance of the circuit can be adjusted wich R604, providing attenuator balance for the 10 m¥/div and 20 m¥/div positions.316 B24. 3.2.5, 3.2.65 B27. Pre-anplifier (unit A5) The input stage formed by D601 (5 transistors) is switched in a Cherry- Hooper configuration and direct coupling is employed throughout. In the positions 20 mV/div. ~ 10 V/div. of the AMPL/OIV switch §8, contact K601 is open and the gain is determined by R626 + R632. approx, REIT + REIZ ~ SPPFORs 148 & IE K601 is closed ( in positions 2 nV/div., 5 m¥/div. and 10 mv/div ) the gain of this stage is increased by a factor of 10. This is accurately adjusted with R621. To prevent jumping of the trace when K601 is switched with the input short circuited, no voltage must be present across these contacts. R604 (attenuator balance) serves this purpose. RE in conjunction with R622,R623 R624 and R626 forms the vernier control. In the calibrated position (R8 is 1 koh) the transfer of this network is 0,85 x. With RB to its atnimum position (0 ohm) the transfer is 0,3 x. Thus we have a control range of 3 x. V608, 609, V613, ¥6i4, ¥616 and V617 form a symmetrical cascode circuit supplying en output CURRENT to the channel switch. the transfer conductance of this stage ts: Tout = = 7 0A/v 1 Win RAT /7 (ROSTFRESE) 77 (ROAGTREAT+REGE) The signal level at the input of this stage is approx. 26 aV/div equivalent to approx. 170 jus/div. at the output. Not ‘The channel A gain can be equalised to the channel B gain with the aid of R543 (gain x I in channel A amplifier). Trigger pick-off (unit 45) The trigger signal is picked-off at the emitters of V608 and V609, a signal source with a low internal resistance, by the series feed-back stage V6ll and Y612, From this stage the trigger signal current is fed asymmetrically to the trigger selector via a 50 ohm cable. ‘The 3 channel has a provision for inverting the polarity of the Y signal. Push-pull switch 84, PULL TO INVERT B, {s mounted on the shaft of front-panel control 3 POSITION. In the Lavert position of the switch the normal signal paths are blocked because V613 and V614 are switehed off. Inversion is achieved by V616 and V617 providing alternative paths for the signal when their bases are switched less positive by $4, Possible unbalance betweea the two positions of the switch can be compensated by preset potentiometer 2647 (Nora tavert balance). Position control (unit a5) Potentiometer R} is the vertical POSITION control. Its balance is adjustable by means of R674 (shift balance).3.2.8. 347 Analog channel ewiteh (unit A5) The ANALOG CHANNEL SWITCH consists of two circufts (SWITCHING AMPLIFIERS) which are inserted in the A and B channel signal paths. The A channel circuit consists of the transistors V524, ¥326 and the @fodes V521, ¥522 and V523. The B channel cireutt consists of the transistors’ V624 and ¥626 and the diodes V621, V622 and V623. liken the junction of the three diodes is positive in relation to mass, the dtodes are non-conductive, The transistors, and thus, the signal pata are conductive. Ue the current drained from the junction exceeds 6 xA, the diodes are conductive and the transistors are turned off. The circuits are driven from the flip-flop formed by the transistors 703 and ¥704. With (SIA) depressed: only channel A is displayed. The base of ¥703 is connected to the ~12V supply voltage. V703 is curned-off then, its collector voltage is high and channel A is switched on, AE the same monent channel 3 is switched off. With ALT (818) depressed: channels A and B are alternately displayed. This pushbutton is a dumay and has no contacts, but {t releases all the other pushbuttons of the display mode controlg. In this mode there 4s a DC path via W704 between the two emitters, the cireutt is bi- stable and one of the diodes is conductive. ¥1201 in not conducting in ALT mode and negative going alternate pulses derived from the time~base generator are fed to the circuit. These pulses switch the cireuit at the end of each aweep and the channels A and B are alternately displayed. oy | nv fe et way FIG, 3.4, Simplified diagram of the analog channel switch.318 3.2.9. 3.2.10, In the ALT node -12V is aplied vis SIA, SIC, SID and SIE and R710 to transistor V1SC6 in the bean blanking amplifier. This transistor is the blocked and the only control signal for the bean unblanking amplifier {s the normal unblanking pulse comiag from the time-base circuit. With CHOP (SIC) depressed: channels A and B are chopped. Im this mode the circuit acts as a chopper generator. SIC is open then, the DC path between the emitters of V703 and V704 is faterrupted and the circuit {8 a-stable. Both diodes ¥701 and V702 are then turned-off and the circuit starts oscillating, the oscillating frequency being approx. 500 kia. During the switching transients tn the CHOP-mode, the C.R.7. is blanked with the aid of differentiated chopper blanking pulses (at the Junction of R703 and C762) which ate fed to the Z-amplifier. With ADD ($1D) depressed: channel A and B are added. Roth transistors are turned-off, both collector voltages are high and both channels are switched on, With B (SIE) depressed: only channel B is displayed. The base of V70s is connected to the -12Y supply voltage. ¥704 is then turned-off, its collector voltage is high and channel 8 is switched on. At the sane moment channel A is switched off. ¢ and D channels (unit Al2 - diagram 2) In MEMORY ON mode two more channels C and D can be added to the system, selected by the ABCD CHOP pushbutton, resulting in @ total of four channels 4,8,C and D. Both channels C and D are identical, each conprising two separate in~ put BNC’s, mounted at the rear of the instrument, with a fixed deflection coefficient of 0,1V/DIV and 1¥/DIV. Furthermore an IMPEDANCE CONVERTER and an AMPLIFIER with a screwdriver FOSITEON control (R13 for channel C and R14 for channel D). Digital changet switch (unit A9 ~ diagram 3) Each AMPLIFIER is followed by a SWITCHING AMPLIFIER which is controlled by a DIGITAL FOUR CHANNEL SWITCH. The ANALOG CHANNEL SWITCH Is blocked in MEMORY ON mode by signal DIGOH via D1802, D1903 and transistors V1901 and V1902. Its function is taken over by a DIGITAL FOUR CHANNEL switch which is controlled by the switches A-ALT-CHOP-ADD-B and ABCD CHOP via the mleroprocessor system. ‘The DIGITAL CHANNEL SWITCH is enabled by the signal DIGCH frou the microprocessor and controlled by the signals CHOPI and CHOP2 from the CHOPPER LOGIC on unit All (see section 3,7.6.). In decoder D1901 four select signals are generated as follows: chop? | cHopi | outpur 0 0 GHANA 0 1 CHAN 1 0 cHANC 1 1 GHAND Signals CHANA and CHANB are then via FET 1903 applied to the cathodes of V523 and V623, thus controlling the channel A and B switching anplifiers. Signals CHANC and CHAND are directly applied to the channel ¢ and D switching amplifiers.319 3.2.11, Delay line driver (unit A5) and delay Line (unit a7) 3.2612, 3.2613. The resulting output signals of the four SWITCHING AMPLIFIERS are Supplied to the DELAY LINE DRIVER and DELAY LINE to the Digital storage cireuits. ‘Tae symmetrical delay line is sandwiched between a series feed-back push-pull amplifier (called CHERRY) and a shunt feed-back push~pull amplifier (called HOOPER), consisting of integrated circuit DBO]. Such an amplifier combination is called “CHERRY-HOOPER' The series feed-back stage receives a signal of approx. 30 nV/div which Ls obtained fron a signal current of 0,17 mA/div. from the channel switch, multiplied by the value of the Load resistance R803 + R804 = 200 obm. The emitter impedance of the sertes feed-back stage consists besides RE = RBIS + R821 of the parallel circuit of a number of RC uetworks. As the delay line is a source of distortion for higher frequencies, these networks are realizing the necessary delay Line compensation. At the input side, delay line D802 terminates in R828 and RB29 (totally 200 ohm). The delay line itself {e a symmetrically mount epfralized cable with a characteristic impedance of 200 otm and a delay of 110 ns/m. At the output side, the cable terminates via R831 and R832 in the virtual earth points of the parallel feed-back stage (HOOPER). The fnput impedance on these virtual earth points is 14 ohm. This value in series with the 86,6 ohm of R 832 and R832 forms the correct termination for the delay line. Composite trigger pick-off (unit 45) ‘The composite trigger signal is picked-off at the emitters of the CHERRY stage (D80I), a signal source with a low internal resistance, by the series feed-back stage V802 and V803, From this stage the composite trigger signal current is fed asymmetrically to the trigger selector via a 50 ol cable. Digital storage circuits (units a9 - Al0 - All) The output signals from the DELAY LINE CIRCUIT are connected to the digital storage circufts. Depeading on the selection of MEMORY OFF or MENORY ON che signal is plied via the so-called “analog signal path" or the so-called “aigital signal path", Selection of the analog signal path means that the DELAY LINE output is directly coupled to the input of the Y FINAL AMPLIFIER via the ADAPTION unit 43. Selection of the digital signal path means chat the DELAY LINE output is coupled to the ADAPTION circuit on unit a9 and then to the MIN/MAX vait ALO, After passing this unit che signal is digitized and afterwards stored on LOGIC UNIT All, For display on the C.R.T. screen the stored signal information ts converted into analog again and then applied via ADAPTION uait 49 to ‘the FINAL Y AMPLIFIER on unit A5. For wore decalled information about the digital storage watts 49 - 410 and All see section 3.7.320 B.2elae Final Y aaplifier (unit A5) The output signals of the HOOPER stage are applied to the FINAL ¥ AMPLIFIER stage consisting of the transistors V804, VB06, V807 and 808, which are configurated as two series feed-back azplifiers in parallel fed by a constant current source. The gain of the FINAL ¥ AMPLIFIER can be Set by means of potentiometer RB4B. The centre taps of the coils [801 and L802 are connected to the Y deflection plates of the C.R.T. The ¥ deflection platec form filters together with the cofls 1801 and 1802, These filters terminate in resistors RB59, R861, R862 and R863.3.3. Bde 3.3.26 3.3636 3.3.4 321 TRIGGERING (Diagram 4) The trigger source switches for triggering the time-base generator, can select any of the following input sources: = an internal signal from the vertical A channel = an internal signal from the vertical # channel = an internal composite signal of channel A and channel 8 ~ a signal derived from the uains supply = an external source an external source divided by id AIL these sources can be used for both triggering and X deflection purposes. Source selection is done by means of a trigger selector switch $16 that feeds the trigger signals to the trigger amplifier. Trigger source selection and preamplifier (unit a3) ‘The signal curtents (60 juA/div.) of the three trigger pick-off stages are, after selection by S16C and S16D, anplified to a level of 100 aV/div. by a shunt feed-back stage + emitter follower stage consisting of V351 and V352, After this stage there is a selection between its output signal, a signal on the extetnal socket and a signal with the line frequency by means of SI6A and S168, Signals that are not used are short-circuited to mass. The externally applied signal is attenuated by a factor of two or twenty (depending on position of EXT and EXT + 10) allowing standardisation of the input impedance of the EXT socket to 1 Mohn // 20 pF. Inpedance converter (unit AS) The trigger signal of 100 aV/div. Is fed via the AC-DC coupling switch $2C to a FRT (¥1006) in source follower configuration. From here the signal is applied via an enitter follower to the + slope selection switch 83. This selection switch enables triggering on either the positive-going or the negative-going edge of the triggering signal. ‘Trigger comparator (unit AS) From the + slope selector switch $3 the signal is fed vie a common eaitter amplifier D100] (123/345) to the output shunt feed-back auplifier VIC14 via the TV mode switch S2D. The voltage gain is high (28 x) but its dycamie range 4s small (2,8 Vp-p at the output). This is because of the tail current of the symmetrical common emitter stage is 2 mA. the current sweep at the output of this stage 1s consequently 2 mA at max. which is transformed into a 2,8 V max. voltage sweep at the output of the shunt feed-back amplifier V1014. This meane that the trigger amplifier is completely driven at a trace height of | div. Which division on the screen this is, depends on the position of the LEVEL, control RS. With ac (S2B) or DC (S26) depressed, the range of the LEVEL control is fixed. The DC voltage at the wiper of LEVEL control RS , which is fed to the FET (¥i006) can vary between + 3,5 Vand - 3,5 Vs Diodes V1001 and ¥1002 ate then turned-off, and the voltage on the gate of the PET is then adjustable between + 0,9 and - 0,9 V. At a signal level on the gate of the other FET of 100 mV/div., there will be a control renge of +9 div. Peak to pesk level detector (unit A5) If the AUTO pushbutton $2A is depressed, the supply voltages for the level control circuit are interrupted,322 3.3.5. A trigger signal (300 m¥/div.) which is derived from the emitter Follower stage and amplified by V1008, gives after peak to peak detection a DC voltage across the level control. This DC voltage is approx. proportional to the amplitude of the trigger signal. This is the auto trigger level control. The peak to peak level of the signal then determines the range of the level control. T.V. synchronisation separator (unit A5) If the TY mode pushbutton S2D is depressed, the LEVEL control is switehed-off. The wiper of 85 is then connected to mass. A synchronisation separator for the television signals is then inserted into the trigger signal path. A composite video signal contains, besides the video information, also synchronisation pulses with line and frame frequency which can be distinguished by their pulse width. ‘The TV synchronisation separator circuit is able to: 1. separate the synchronisation pulses from the video information. 2. distinghuish between fraue synchronisation pulses and line synchronisation pulses. ‘The first requirement is met by V1O13 acting as a DC restorer and Limiter, the secoad requirenent by the integrating network R1047, CIOL and C1012. ‘The TV signal is picked-off at the + slope selector switch which in this case can be set for the right polarity of the TV signal. The TV trigger signal, is then amplified by the series feed-back push-pull stage V1009, VI011 and applied to synchronisation separator VI013 via emitter follower V1012. The signal on the base of ¥1013 could be as barr FIG. 3,5. Signal on the base of transistor VIO13. ‘The peaks of the synchronisation pulses are all at one level by the DC restorer action of C1007, RL039 and the base emitter diode of Vi013. The base voltage will never exceed + 0,6 V by a large amount, but the complete waveform will appear at the base. The signal level is at this point approx. 260 mV per screen div, Change in signal of approx. 100 nV is sufficient to turn off V1013. VIOI3 locks only to the peaks of the synchronisation pulses. ‘The rest of the TV signal has no influence. On the collector of V10L3 we find exclusively the synchronisation signal consisting of line synchronisation pulses and the wider frane synchronisation pulse: Ia the time-base positions 20 jus/div. and faster, this conplete signal is transmitted to the time-base generator and we have line eriggering.323 In the time-base positions 50 jus/div. and slower, C1011 and C1012 are connected to masa. The narrower line synchronisation pulses are then, integrated out of the signal, but the wider frane synchronisa~ tion pulses remain, and frame triggering is obtained. A second thres~ hold is built-up by V1016. ¥1027 reacts to the signal that still passes and consists of pure line or frame synchronisation pulses. After this the signal is fed to the time-base generator via L014. une syve, srg Pee sie AU bes FIG. 3.6, A vertical interval with frame synchronisation pulse group. DUAL SLOPE triggering. Selection of DUAL enables the display to be triggered on either the positive-going or the negative-going edge of the input signal, This DUAL SLOPE trigger mode can only be selected in MEMORY ON. Without DUAL SLOPE triggering selected, the trigger signal from the trigger shunt feedback amplifier VI014 is applied via NAND D1931 (1-2~ 3) and WAND D1931 (11-12-13) to NAND D1931 (8-9-10), which reacts on the positive slope of the signal, to the sweep gating logic. The clreait 1s blocked during the generation of a sweep by the signal oa input 2 of NAND D1931+ With DUAL SLOPE triggering selected, the microprocessor generates a control signal DUALOUT which is applied to NAND DI931 (4-5-6). This circuit reacts on the negative slope of the signal. At the sane time 2 level correction 1s achieved via transistor V1938 and resistor R936.Bebele ‘TIME-BASE GENERATOR (Diagraz 5) The time-base generator comprises a sweep gating logic, a sweep generator, a hold-off circuit, an auto sweep circuit and X final amplifier. Before considering these stages in detail, the general principle is briefly described. Basically, the sweep gating logic, under the control of trigger signals fro the trigget conparator and also feedback pulses from the hold-off circuit, supplies square-wave pulses to the switching transistor V1213 off the sawtooth generator. The time-base capacitors (effectively in parallel with the switching transistor) are charged linearly through a constant-current source to provide the forward sweep, and are discharged tapidly by the switching transistor to provide the flyback period. The resulting sawtooth is fed to the X-final amplifier. Sweep generator (unit A5) ‘The sweep speed or time coefficient is determined by the value of the time-base capacitance in circuit, and also by the magnitude of the charging resistor selected, The time-base capacitors are C1204 and C1207. Capacitor C1204 is always in circuit, the other one is selected by the transistor V1216. This transistor operates as an electronic switch and is either fully cut-off or fully-conducting. It is switched on by the application of a positive voltage to its base from the TIME/DIY switch S10. According to the position of $10, this traasistor V1216 switches in the capacitor C1207 in parallel with C1204. As mentioned, the sweep epeed 1s also dependent upon the magnitude of the accurate constant-current supplied by transistor V1212. This current can be adjusted in steps by selecting the euitter resistance of V1212 by means of the TIME/DIV switch S10. Continuous control of the charging current can be effected by varying the base drive to vi212 with the continuous sweep control, TIME/DLV potentiometer R. In the CAL position of this potentiometer, switch Sl} closes and the charging current is solely determined ty the calibrated emitter resistance. To compensate for the temperature coefficient of the transistor, the base voltage of Vi2i2 is supplied via transistor V1214. This also has the advantage of reducing the load on the TIME/DIV potentiometer R9. This transistor, in turn, has its base controlled by preset potentiometer R1232 when TIME/DIV switch S10 is in one of the positions 0,5 s/div. ... 0,5 ns/div.. This ptovides a fine adjustment for the tining circuit in the slower sweep speeds, In these positions the preset potentioneter R1232 provides an additional measure of control over the base voltage of Vi2i2. In the positions of $10 when €1207 is not in circult, the diode ¥1218 is blocked and the preset control R1232 is inoperative. ‘The discharge circult for the capacitors (1204 and C1207 consists of resistor R1219 and transistor V1213, This switching transistor is driven by the sweep gating logic via a number of diodes. Diodes V1207 and V1208 form an AND-gate for positive logic. ¥1209 and V1211 adapt the level to control transistor V1213. The resulting sawtooth voltage is taken from two transistors V1219 and Vl221 in a kind of Darlington pair configuration. ©1209 improves the transfer of faster sawtooth signals at the expense of the input impedance which need not to be that high thea, The sawtooth voltage aaplitude is approx. 5V. This sawtooth voltage is then fed to the X-final amplifier.Behe Bebe 325 This sawtooth voltage 1s also applied as signal SaWTH to the conpa~ rator D2016 in the digital storage circuits. Tt is then used In MEMORY ON mode for the sequential sampling mode. Hold-off circuit (unit A5) The hold-off circuit prevents the sweep gating logic from responding to trigger pulses before the time-base capacitor has fully discharged. The sawtooth output fron the Darlington pair ¥1219 ané ¥1221 is applied to the base of emitter follower V1223. ‘The switching transistor VI217 switches the hold-off capacitor C1208 in eireait, paraltel to C1206, according to the position of the TIMB/DIV switch S10, in 2 similar manner to that described for the time-base integrator timing capacitor. Capacitor 61206 is always in cireuit irrespective of the TIME/DIV switch position. Charging current for the hold-off capacitors flows via transistor V1223. When V1223 cuts off the discharge current flows tarough R128 and held-off control R12, This curreat 1s aéjustable to change the hold-off time. The voltage across hold-off capacitor C1206 or C1206 + 1208 follows the sawtooth voltage fairly fest in positive going direction via enitter follower V1223, When a certain value is reached, integrated Schmitt-trigger D1201 reacts and the end of the sueep is inttlated. This is followed by a hold-off yertod in which the voltage across the hold-off capacitor decreases fairly slowly until the lower switching level of the Schmitt trigger {s reached. The system can now be triggered again. In the mean-time also the time-base integrator timing capacitor C1204 or C1204 + C1207 has reached its quiescent state. The output (point 6) of D1201 is low during the hold-off tine, at any other moment this output is high. Sweep gating logie (unit a5) The sweep gating logic which consists of TTL logic circuits ts controlled by the following signals: = The trigger signals supplied by the trigner comparator. ~ The voltage supplied by the hold-off circuit, ~ The voltage supplied by the auto circuit via the hold-off circuit. ‘The TTL circuit D1201 contains four 2-input NAND-gates with Schmite= trigger properties. D1202 contains four normal 2~tnput NAND-gates and D1203 contains three normal 3-input NAND-gates, With the aid of the various gates tvo flip-flops are formed, See for the following explanation time relation diagram FIG. 3.7. L The tacoming trigger signal from the trigger comparator switches the Schnite-trigger output (01201, point 11) to aero after a positive going edge has exceeded the upper switching level (+ 1,7 ¥) of this Schmitt-trigger. 2 After this, the first flip-flop output (D1202, pofat 3) ts set to the logic I-state. 3 If the negative going edge of the incowing trigger signal drops below the lower switching level (+ 0,9 V) of the Schmitt-trigger, the output (D1201, point 11) switches to logic 1 level again,328 aime aoe LP rao, oom oy FIG. 3.7, Time relation diagram of the sweep-gating logic in the 443,68 10 u AC or DC mode. The logic 1 state of the first flip-flop and the output signal of the Schmitt-trigger allows the setting of the second flip-flop output (D1203, point 6) to the zero state by means of the NAND output (D1202, point 11). The output signal of the second flip-flop is applied to switching transistor VI213 via an OR-gate which consists of R1216, V1207 and V1208. This signal causes the sweep to atart. The end of the sweep is reached when the signal across the hold-off capacitor 01206 exceeds the upper switching level (+ 1,7 V) of the hold-off Schmitt-trigger. The output of this Schnitt-trigger switches then to zero, Both flip-flops are now reset. Switching transistor ¥1212 starts conducting and tine-base capacitor C1204 will dis- charge. The voltage across the hold-off capacitor C1206 decreases slowly until the lover switching level (+ 0,9 ¥) of the Sctmitt-trigger is reached. This is the end of the hold-off period. The output (D1201, point 6) of the hold-off Schmitt-crigger rises to 1 again and the system can be triggered again.34. Behe 327 Auto sweep circuit (unit a5) In the absence of a trigger signal and with AUTO selected we would still Like to see a display on the screen. The auto sweep circuit serves this purpose. After selection of the AUTO uode (AC and DC off) the voltage across capacitor C1202 starts Increasing until after approximately 100 ms., transistor V1204 starts conducting and causes transistor ¥1206 to conduct. ‘The collector of ¥1206 rises to approximately + 5 Vand the signal AUTO will be logic "I". This is seen by the ju? which in tura makes signa! HTRG logic "1", The hold~ off signal o& point 6 of D1201 can now reach via gate DI201 (3) and the OR-gate, the switching transistor Vi213. The loop ts then closed and the time base generator is in the free running mode. 4s soon as trigger pulses are available, the free-running state of the time~base generator is autowatically termiuated and normal triggering is tesuned. Final X amplifier (unfit as) For nora) tine~base operation (MEMORY ON released) the FINAL X AMPLI- BIER is fed by sweeps from the TIME-BASE circuit. Transistor V1407 is then driven by the time-base generator via diodes V1411 and VI409 when R1406 is kept at + 12 V level TINE/DIV switch S10 (an all the TIME/DIV positions of this switch). With the TIME/DIV switch in the XDEFL position horizontal deflection from an other source than the ‘time~base output is permitted. The amplifier stage ¥1404 when RIGO? is then kept at + 12 ¥ level via TIME/DIV switch S10 (an position X DEFL). Transistor V1404 receives {ts input signal from D1001 point 8 of the trigger amplifier. This signal is derived from one of the sources, channel A, channel B, Line or an external source, depending on the setting of the X deflection selector switch S16. ‘The final X amplifier consists of two amplifier stages in parallel (one for each deflection plate). Only one half is described. The actual amplifier is the cascode circuit with transistors V1414 and v1é16. ‘The resistors R1428 and R1429 are feedback resistors. The bias current for the amplifier is supplied by transistor V1413, The average voltage on the deflection plate is kept at + 26 V by means of zener diodes V1424 and V1426. Capacitor C1413 improves the kf. response. ‘This final stage is supplied from the + 180 ¥ and - 180 ¥ because the X plates of the C.R.T. are mechanically displaced such that they ace dess sensitive than the ¥ plates. The cascode amplifier stages are controlled via the transistors 1406 and VL407. The bias of transistor V1406 can be varted with the X POSITION potentioneter R4, which consists of a tandem potentiometer with back- lash, giving a nice vernier control, Variation of the bias causes the balance of the amplifier to be diecurbed, which results in a horizontal trace shift on the screen. The X amplifier allows choice from K deflection by the time base Signal or one of the sources, channel A, channel B, line or an exteraal signal. The deflection source is selected with the aid of the TINE/DIV switch $10 and the X-deflection source selector switch Si6. ‘The X amplifier offers the possibility of using either the nominal gain (x 1 position of x MAGN switch $5), or the gain increased by @ factor of 10 (x 10 position of X MAGN switch S5).328 When the front-panel X MAGN switch is operated for 10 x magnification, the emitter resistance RI416 + R1417 of transistors V1406 and V1407 is shunted by resistors R1418 + R419 reducing the value by a factor of 10. Consequently, the gain of the stage is increased by the same factor. The x 1 gain can be set by potentiometer RISI7 and the x 10 gain by potentiometer R419, The x 10 gein 1s also operative when X DEFL is selected. Both outputs of the X final amplifier are connected to the X~ deflection plates of the C.R.T.. With MEMORY ON selected the addresses for the DISPLAY MENORY are converted to an analog staircase signal by the microprocessor con~ trolled X DAC and then applied as signal XOUT to the base of transistor V1407 in the PINAL X-AMPLIFTER via a SMOOTH filter and ADAPTION circuit. At the same time the time-base sweep signal path via dicdes VI411 and V1409 will be blocked by signal SHAR which is applied to the junction between diodes V1409 and 1411. in XeA/Y=5 mode the AVSB and QUARTER logic applies the signal value of ehannel A to the X DAC and the mean value of 2 adjacent channel B values to the Y DAC, This is controlled by the DISPLAY MENORY COUNTER. Now the channel A signal is displayed horizontally and the channel 3 signal is displayed vertically. QUARTER display is realized by the AVSE and QUARTER logic under the control of the microprocessor system. For nore detailed information about the digital storage units see section 3.7.3.56 B.Sele Bu5.2e 3.29 CATHODE-RAY TUBE CIRCUIT (Diagram 6) ‘The cathode-ray tube circuit consists of the C.R.T. and its associated controls: focus, intensity, trace rotation and the beam blanking amplifier. G.R.T. controls (unit 45) By means of the INTENS potentioneter Xl, the brightness of the display can be continuously controlled. ‘The display can be focused by means of the FOCUS potentiometer RS. Both INTENS and FOCUS controls are front panel controls. Furthermore the C.R.T, circuitry comprises preset potentiometers for trace rotation, astigmation and geonetry. The FOCUS control R6 forms a part of a voltage divider network across the 1.5 kV output of the power supply. The slider of this potentioneter is connected direct to the focus, grid G3. ‘TRACE ROTATION is achieved by means of the trace rotation coil 11501. Thts coil mounted inside the mu-metal screen, provides a magnetic field for rotational control of the entire scan. The degree and direction of rotation is determined by the setting of front panel potentiometer R10 (srewdriver operated). The slider of RIO is connected to the bases of the complementary transistors V1521 and V1522. ‘The trace rotation coil 11501 is supplied by these transistors. With the ASTIGMATISM control RI543, the form of the ¢pot can be adjusted by influencing the voltage on the grids G2 and 04. @Q @ Q With the GEOMETRY control R1549 the barrel and pin-cushion distortion is corrected by influencing the voltage on the grid G7. oT ro 4 \ t ! i { Lf L--4 b--4 2 amplifier (unit AS) MAT 16 In MEMORY OFF the Z-anplifier receives two input signals. Ove signal originates in the time-base generator and is applied to the amplifier to unblank the trace during the veep. ‘The other one is supplied by the ANALOC CHANNEL SWITCH to blank the trace during switching from channel to channel in the CHOP~mode. ‘The INTENS potentiometer Rl deteruines the amount of input current fed to the amplifier.330 The 1.f. components of the blanking signal are modulsted and denodla~ ted (for voltage isolation purposes) before they are applied together with the acc. coupled hf, voltage components to the Wehneit cylin- der. In all TIMZ/DIV switeh positions of the TIME/DIV switch S10, the anode of diode V1202 is kept at approx. + 12 V, resulting in a logic 1 level at input 1 of NAND D1203. The output point 12 of this NAND is now at logic 1 level when either input 2 or input 3 1s low. Tn other words only during a sueep. In the X DEFL position of the TIME/DIV switch $10, input 1 of NAND D1203 de at logic 9 level, and in that case the output point 12 of this NAND is steady at logic | level. This output signal is {averted by a NAND and fed via diodes VISOL to diodes V1502 end V1503 of the beam blanking amplifier. The CHOP mode blanking signel from the channel switch is fed to transistor V1506 via R1502. The inverted and anplified signal is epplied to diode V1508, Both signals are joined together at the base of transistor VI514 (point Ain figure 3.8.), This is the virtual earth point of a shunt feedback amplifier. SHUNT FEED-BACK AMPLIFIER vis08 CHOP mode blanking signet Sweep gate i503 INTENSITY, IRV Ri war w7s FIG. 3.8. Shunt feed back amplifier. Assume that V1503 and V1508 are turned-off by applying a logic zero to both inputs. Then the output voltage of the auplifier can be varied with the aid of INTENS potentiometer Rl. The Light on the screen is variable then e.g. during a sweep or in the X deflection mode. A logic 1 on ezther one or both inputs of the diodes ¥2503 and V1508 turns V1511 off. The C.R.T. is then blank e.g, between sweeps or during the sweep when there is channel switching in the CHOP mode. The blanking signal is amplified in the stage with transistors ¥1512, VI513 and V1514. At the output of this amplifier the a,c. and d.c. components of the blanking signal are guided along different paths. The a.c. path runs straight to the Wehnelt cylinder of the C.R.7, via capacitor C1512. A-d.c. signal 45 fed to the emitter of transistor V1517 via a lowpass filter R1526/C1508/R1527, Transistor VI517 constitutes a multivibrator together with transistor VI516. The a.c. voltage on the collector of 1517 has a peak-to-peak value which depends on the voltage fed to the emitter of VI516 by the shunt feed back anplifier. The ase. voltage supplied by multivibrator Vi516/VISi7 is applied to a peak detector, This peak detector rectifies this a.c. voltage.a1 The reason for the a.c. and d.c. paths is isolation of the cathode and Wehneit cylinder, which are on 4 — 1,5 kV potential, from the other circuits. the a.c. component of the blanking signal is transmitted straight away to the high-voltage part via blocking capacitor C512, which 1s a high voltage capacitor. The d.c. signal, however, is converted into an a.c. voltage and then transmitted to the high voltage part, via capacitor C1509,after which it is rectified by means of diode V1519. The dark level can be adjusted with the atd of potentiometer RIS34 in the emitter circuit of transistor VI5I7 in the d.c. amplifier. In MEMORY ON the way in which the contents of the DISPLAY MEMORY is displayed on the C.R.T. screen depends on the functions which are selected by the operator, The contents of the DISPLAY MEMORY are 4096 words, each consisting of 8 bits, Each g-bit word is capable of indicating 256 different anpli- tudes (ive. 2° = 256) : Y values. Bach address of the menory corresponds to a by the selected function specified vertical line of the display along the X-axis. The 4000 words of the DISPLAY MEMORY contents of 4096 words are déis- played in a display area of aore than 8 vertical divisions and 10 hori~ zontal divisions which is divided into 256 x 4000 dots. (96 dots are displayed outside the 10 horizontal divisious). A juP-controlled DISPLAY COUNTER sends 4096 different addresses sequentially (starting with address 0 and ending with address 4095) to the DISPLAY MEMORY and to the Digital-to-analog-Coaverter (DAC) of the Xesystem, To provide the discrete steps for the horizontal time-base display the output of the X-DAC (signal XOUT) is a linear staircase voltage, which is applied to the FINAL X-AMPLIFTER. ! / vISeLAY MeWoRY ( ans — [ADDRESSES GF ARM NEWRY OVER TOI THER GS Acoma FIG. 3.9, Complete display of all the values of one channel. Simflarly, the 8-bit instantaneous values for each address (i.e. the ¥ information) are converted into analog signals by means of the Y-DAC, The converted signal is then applied to the FINAL-Y-AMPLIFIER,332 3.563. In MEMORY ON mode (signal ZMODE is active) the blanking pulse ZMOD for the different display modes is generated by the display menory logic. ‘This 2MOD pulse is guided via NAND D1203 to the cathode of diode vI501. Galibratoc (unit a5) ‘The caltbrator circuit consists of transistors Vi601 and V1603, which are configerated as a stable multivibrator such as used in the channel switch. Good shape of the wave-fora is obtained by a constant current supplied by transistor V1602 which will flow in curds through the left hand or right hand transistor. The anplitude is 1,2 V or 6 div. in the 20 mV/div, attenuator positions. (The straight through position of the attenuator) « Potentiometer RI607 allows accurate adjustment of the amplitude of the calibrator output voltage. This square-wave output voltage is taken off from the collector of transistor V1603 and fed to socket Xl. ‘This is the front panel CAL terminal. The calibrator output signal can be used for probe compensation and/or checking the vertical deflection accuracy.3.6. 3.6.16 3.6.25 3.6.34 33 POWER SUPPLY (Diagram 7) General ‘he power supply is designed on the switching regulator principle and permits the instrument to be connected to nominal maing voltages of 100V, 120¥, 220V or 240V by switch selection, or to an external battery supply of 24.4427 Ve The mains supply via POWER ON switch $17 is protected by fuse F202, The battery input is protected by fuse F201 and diode V206 safe-quards the circuit against reversed battery connection. Basically, the power supply consists of: - Mains transformer - Converter and stabilized power supply - Mlusination efreuit Mains transformer (unit Al) An incoming mains voltage is fed via the thermal fuse (FIO1) and the voltage selector $101 to the appropriate primary taps on the mains transformer T101. Transformer T1O1 has three primary windings which can be combined by means of voltage adapter S18. This combination allows the instruneat to be used with mains voltages of 100V,120V,220V or 240¥. The voltage on the secundary windings of this transformer is full~wave rectified. The resulting negative d.c, voltage (approx. 24 ¥) across electrolytic capacitor 0203, or alternatively a negative d.c. voltage on the rear panel DC POWER IN input socket Xl1, is applied to the voltage stabilizer and converter. Part of the a.c. voltage on the secundary winding of the mains transformer is fed via C201, R473 and R372 to LINE trigger source selector switch $164, to enable internal triggering on the Line Frequency. Gonverter and stabilized power supply (unit Al) The converter is a squate-wave gencrator operating at a frequency of approx, 18 kHz and driven by the d.c, voltage across the electrolytic capacitor 0203. A basic diagram of the converter is shown in figure 3,10. Jt ort FIG, 3410, Basic diagram of the converter.In the converter, transistors V217 and V218 function as switches and regulators and alternately connect the negative supply voltage to either end of the primary of 1201/1202. Assume that transistor ¥Z17 has a slightly higher current gain than V2i8. Then the positive voltage from the feedback winding quickly drives transistor V217 into saturation, The current in the top half of the primary of T201/T202 increases linearly at a rate determined by the inductance of the primary. This current increase continues until the iron in transformer coil 201 is saturated. Then the magnetic lines of flux stop changing and consequently no voltage is Induced any longer in the feedback winding. When its base drive ceases, the transistor 4s cut off, This veverses the polarity of the feedback voltage and transistor V216 is turned hard on. The bottom half of the primaty then passes an Ancreasing current until the core is saturated in the opposite direction. ‘The subsequent absence of feedback voltage initiates the switching back to V2I7 and the cycle starts again. The regulation works as follows. When an input voltage is applied to che converter, the nogative voltage across Zener diode ¥209 turns transistor ¥2i6 fully on, as there is no positive voltage from Conperature compensation stabistors V211 and V212. Then 2 bias current flows via transistor ¥216 through resistor R207, through the base-emitter junction of transistor ¥214 (operating as 4 diode since diode V213 interrupts the collector cirevit) and from base to emitter of both transistors V217 and V2i8~ As there is chen an a.c. voltage across the primary of 1201/7202, diodes ¥222 and ¥223 produce a positive d.c. voltage of + 20 V across capacitor C209. This voltage reduces the current through transistors v2l6 and V2i4 sufficiently to itmit the drive to transistors V217 and v2i8 and produce the desired output level. The setting of potentioneter R204 determines the value of the regulated output voltage. Possible differences from the set outpet voltage are fed back via the temperature compensation stab{stors V211 and V2I2 to teansistor V216 so that the drive of transistors ¥217 and 218 le adapted so as to compensate for the differences. This also applies to mains voltage fluctuations. After rectifying and suoothing, the secundary voltages + 5V, + 12V, - 12¥, + 3BV, + 180V, ~ 180V, - 1500V and post acceleration voltage + 8500V are obtained. The voltage quadrupler which supplies the + 8500 V cannot be repaired and must be replaced when it breaks dow. 71202 contains a separate secundary winding for the heater voltage for the C.R.T. ALL supply voltages except the + 8500V and the ~ 1500 can be continuously short-circuited without danage to the components, Resistor 202 limite the collector current when the outpet is short cireuited and the switching action 18 stopped, thereby holding the dissipated power in transistors V217 and V2I8 at a safe level. Thus, the power supply of the oscilloscope is fully protected against short-circuts, A short-circuit {s indicated etther by a squceking noise coming Erom the power supply or by the pilot lap BL, which indicates the ON state of the oscilloscope, failing to Light up. TE supplied by an external dc. voltage, the instrument is protected against overloads and wrong polarity by internal fuse F201 and diode 206.366.4. 3.6.54 235 Illumination circuit (unit Ab ~ Diagram 7) The graticule of the C.R.T. can be illuminated by means of the bulbs BL, The intensity can be varied with the aid of ILLUM potentiometer RL1 which controls the collector current (which is the current through the bulbs) of transistor V207. The illumination circuit is not short— circuit proof. + SV DC unit (unit 48 ~ diagram 7) ‘The voltages on points A, B and C on the secundary windings of transformer 1202 are applied to a separate 5V DC unit (UNIT AB). These voltages are full-wave rectified and the resulting positive end negative d.c. voltages over capacitors C252 and C251 are applied to Logic unit All.336 3.7 BeTade 3.7.2. 3.72.16 DIGITAL STORAGE CIRCUITS General ‘The digital storage circuits consisting of the ADAPTION unit A9, the MIN/MAX unit A10 and the LOGIC unit All are described now. Because the complete system is controlled by a microprocessor control systen, firet this system will be described. Microprocessor control cireuit (unit All ~ diagram 8). Input shift register. ‘This circuit consists of four digital shift registers D2011, 52045, 2078 and D2104 which are connected in serial. The data inputs are connected to the front panel switches of which the settings must be known by the microprocessor system. Input switches and signals: MLO A~ALT-CHOP-ADD-B settings from the vertical OM mode switch $1 of the analog oscilloscope ML part. emo [ cata [ cM, A o ° 0 ALT I 1 1 cHor 1 ° 0 ADD 1 1 0 B 1 L Q ‘DuaL aN Signal from DUAL SLOPE switch $32. AuTO Signal from collector V1206. raz 733 TB Signais from TIME/DIV switch S10. 735 736 737307 x | x | t2)t83 [186] r55] 16] r37 afi] ofojols:]1) o jo,ajussesv. afi }ofo}ila| 1 | o o,2/us/eiv. rai ]fololijr ya] a joyspusreivs r}1}ofo}olola}a} ayusei, ria }ofufolo}iti| aerate. yi ]ofifolo}o fi] sjusfaiw. tia jafof}ojo}o} 1) r0us/aiv. r]i]2}o}o]}ifo]1 | 20;us/eiv. r}i | ofr joqi fo] i | sojussaiv. rfa}oaltfofo}i fo | otmssasv. rfi|afafafofa|o | ojamssaiv. rfi | r}ififofo |e | cjsmssaw. fxr} a}ifolofo}o]} aras/av. afi} afi fojofo}i| ams/aiv. tfrj}a}ifijolojat Snsfaiv. afi puto li foto }o | tomsaiv. a}1 | afojr]|ujo}o] 2omsseiw. r}r foto ji fi fo fo | soms/aiv. rfi fo oli fo fr fo] orssase. ry fo fr |i foi jo] o,2s/aiv. rfi fo fr fafa fo lo] osssaiw. sMooTH ABCDGHOP MEMDUMP MIN/MAXL XeA/Y=B TIMa/ DIV PRETRIG o8F quar COMPARE Lock CLEAR RESET SINGLE ‘STORE Shift register parallel operation: Uf signal LIXT (load text) = logic "1", the input signals on the data inputs are latched into the digital shift register. Shift register serial operation: when the microprocessor places address 8000H on the multiplexed address/data bus, the TO8 signal is going to logic "0". The TOE signal combined with RBI results in TORDS which is used as Clockpulse for the _shiftregister. The register reacts on the positive going edge of the IORDS signal. To read the complete shift register contents by the microprocessor system, 32 clockpulses (32 x IORDE) are needed.36722626 As result an output eignal SHROUT (shiftregister output) is applied to the INPUT LOGIC circuit D2116. Furthermore the signals STORE aad SHAR are derived from the MEMORY ON pushbutton on the front panel. Signal SHAR (store-hardware) is on a + ot - 12 V level to switch the diode switches on the amplifier board and ts converted into a signal STORE with TTL level. Microprocessor system. ‘The microprocessor system basically consists of the following circuit elements: ~ Aatcroprocessor for controlling and organizing data flow. (8085 ~ 2121). - Erasable and programmable read-only menory (EPROM) for system programming. (D2082) + ~ Integrated peripheral circuit with randon access menory (RAN) with 1/0 ports and TIMER. (B155H2 - D2064). ~ Address selection latch for the address~bus. (7418373 ~ D2096) ~ Decoders for RAM and ROM selection and address decoding. (7418138 ~ 02113). = Two way buffer to the system data-bus. (7418245 - D2101). ~ Trivstate buffer to the systen sddress~bus. (74LS244 ~ D2122/D2127). = Input port. (7418244 - D2116). = Two output ports. (7418373 - D2116/D2117). = Shift register and LED BAR UNIT, (741S164 - D541). The heart of the qicroprocessor control circuit is integrated circuit D2121, an 8-bit microprocessor type 8085 with 16 address lines. The First eight address lines are time-multiplexed with the eight data lines and are defined as ADO ... ADT. Demultiplexing is performed with the ald of the signal ALR from the 8085. The groups of output signals AUPO .., AUP? and AUPS ... AUPIS constitute the address bus. ju? existal connections X and X- A 5 Miz crystal is connected to the clock inputs x; snd X) of the microprocessor to provide an accurate timing reference source. je? RESTA input After switching ON a reset level of logic “0" is available on the RESIN input. This resat signal forces the microprocessor to initiate the main programa, beginning at the address 0OO0K. After a certain RC-time the reset level becomes logic "1" and the microprocessor is ready for use. yee sip (Serial input data) The microprocessor will receive on thls SID input the information from the SERVICE jumper. ye? 80D (Serial output data) ‘The microprocessor generates on this SoD output a software trigger for the Service Routines.399 Connection to the internal address~bus via the address latch D2096 ‘The first eight address bits placed by the microprocessor on its multiplexed adéress-data bus lines ADO ... AD7 have to be separated fron the eight data bite. This is achieved by address latch D2096. Demultiplexing is performed with the aid of the signal ALE from the 8085. The groups of output signals AUPO ... AUP? and AUPB ++. AUPIS constitute the address bus. Connection to the system data~bus via the bidirectional date buffer p2l0l. The eight data bits from the microprocessor have to be coupled to the system data bus. This coupling is done by the bidirectional data buffer D2101- This buffer is selected 1 DATUPC 1s logic "0". Input or output data depends on the logic level of signal RDUF. RDUP = logic "1" means OUTPUT RDUF = logic "O" means INPUT Data is transported between the D2101 in- and outputs and the system data-hus over the lines DO... D7. Connection to the systen address bus via the tri-state buffer D2122 + 2127. ‘The address bus Lines are connected to the system address bus lines AUPBO .., AUPBI1 via the tri-state buffer D2122 + D2127, ‘The lines AUPBO .., AUPBI1 are applied to the DISPLAY MEMORY for DATA handling. Signal DATUBC is then low.SYSTEM MEMORY NAP FFFFH BOCON DFFFH coon BRFFE 0008 OFFPH 80008 TEFFR 60008 SPFFR 40008 SERRE 2000H Leer 000K TOE Romi (not used) Romo ‘EEE OPTION OUTPUT PORT OUTPUT PORT INPUT LOGIG (RD) ign BAR CHR) 7000H COMMAND 7O01R PORT A 7902R PORT B 60008-60FFH RAM BiS5R2 — 02064 i i : 3 g 70034 PORT C 7004H TINER (LSB) 7005H TIMER (MSB)341 ADDRESS DECODING ROM ~/uP RAM -I/0 ports-DATA selection. In decoder D2113, 6 select signals are generated as follows: AUPIS | AUPI4 | AUPI3| Output | Addresses signal 0 | ROW | COOOH-IFFPH | ROM select signal. ROMI | 2000H-3FFFH | Not used. o | Dar 4Q00K-SRFFH | DISPLAY MEMORY select signal for /uP coutrol of DISPLAY MEMokY. 6000K-6FFFR | RAM select (8155) —— | 2000i-7FFFh | 1/0 select (8155) 1 ° 0 | F08 | s000H-9rFFH | Select for input logic + led bar + start input and display cycle. al L ° 1 | TOA | aoo0u-BFFFH | 1/0 select signal. 1 1 0 | Toc | cooox-prevH | 1/0 select signal. 1 1 1 | TOE | EOOOH-FFFFH | Select signel for IEEE option. The following select signals are derived from the output decoder 1/0 select signals 108 ~ TOA and ToC. 108 —> IORDS points to INPUT LOGIC (Read action). > TORRE points to LED 3aR UNIT and stare input and _ display cycle. (Write ection). TOR —-> TOWA points co OUTPUT PORT (Write action). TOC —-> TOWRE points to OUTPUT PORT (Write actton). 3 ROM MEMORY ‘The ROM (read-only memory), which contains the syste programm, consists of the EPROM chip D2082 of 4k bytes (4096 x 8 bits). If an IEEE-688 option is installed, an EPROM of 8X bytes is used. ‘The reserved ROM addresses are OOOOH up to IFFFH. Because the microprocessor’s first eight address lines ADO ... AD7 are tine-multiplexed in the microprocessor with the data lines, the addresses have to be latched by the address latch D2096 on the ALE signal, ‘These signals are placed on the nicroprocessor board internal address bus lines AUPO ... AUP7. Zach RON memory address can be selected by the address lines AUPO ... AUP7 together with address lines AUP ~ 9 ~ 10 - Li and 12, ‘Tae ROM memory chip ts selected by the read signel RDUP and the ROM selection signal ROW. When a certain ROM address is selected in this way, the contents of the selected location are placed on the data bus lines DUPO ... DUP7. JAP-RAM MEMORY ‘The /uP-RAM (microprocessor random access memory) is used by the microprocessor for stack purposes and for storage of variable data. It is a part of the chip D2064 (8155H2) which is a RAM + I/O ports + TIMER. The RAM consists of 256 x 8 bics.342 Each /uP-RAM memory address can be selected by the internal data/address lines DUPO ... DUP7 on the signal ALz. ‘The RAM is selected when the signals GEP and AUPI2 are logic Reading the RAM contents or writing data into a RAM location ts controlled by the signals RDUP and WRUF. The data to be written into, of read from the RAM menory is also transported via the multiplexed adéress/data bus DUPO ... DUP7. INPUT LOGIC When the microprocessor places the address 8000 on the multiplexed address bus, this results in signal TO8 going to logic "0". This 108 combined with the RDUF signal to TORDS enables the INPUT LOGIC buffer D2116 to place its input data byte oa the internal data/address bus lines DUPO ... DUP7. This byte consists of the following signals: Bit 0 TRGRD ‘Triggered. Bit 1 EINE End input. When "0, input cycle is going When "I", input cycle is ready Bit 2 ExXTCL External clock. Bit 3 DT Displey timing pulse. when "0", display cycle is going When "1", display cycle is ready Bit 4 INT(option) Interrupt from IEEE option. Bit5 +54 Not used. Bit6 +5¥ Not used. Bit 7 SHOUT Input shift tegister output signal containing the setting of the front panel switches which are communicating with the /uP. OUTPUT PORT 2118. When the microprocessor places the address AQOOH on the multiptexed address/data bus, this results in signal TOA going to logic "0". ‘This TOA signal combined with the WRUP signal enables the data latch (output port) D2118 to latch the byte of data present oa the multiplexed address/data bus. ‘The data byte consists of the following signals: Bit 0 | STADO Bit 1 STADE 3 LeS.B./s of the start address (£0F 1,2,4,0r 6 Bit 2 stap2] for the display counter. trace display.) Bic 3 STADE Bit 4 sraploh 3 ¥.3.B.’s of the start address (#0r quarter Bit 5 STAD1I] for the display counter. display.) Bit 6 Control signal for the NOT TRIG’D lamp. Bit 7 Control signal for the REMOTE lamp. OUTPUT PORT D2117. When the microprocessor places the address CO00H on the multiplexed addrese/date bus, this results in signal TOC going to logic "0". ‘This TOC signal combined with the WRUP signal enables the data latch (output port) D2117 to latch the byte of data present on the aultiplexed addtess/data bus.The data byte consists of the following signals: Bit 0 TBT Signal to block the time-base TIMER OUT signal in 0,2ms/div., Q,5ms/div. and lms/div.. Bie L TBC } TB:2/:5/210 [PBDI TRC Bit 2 TBD po y= ofiq= ofol- Bit 3° PRTRO) © PRE~TRIcceR —«[PRIRZ[ PRIRITPRIWO Bit 4 PRIRI> LENGTH a Bit 5 PRIR2 bofr jo j= aa 1 |o Jo jeae2 o |i fo |= 3/4 o Jo jo |=1 Bit 6 Control line for the REP ONLY lamp. Bit 7 Not used. LED BAR UNIT When the microprocessor places the address 8000H on the multiplexed addzess/deta bus, this results in signal TO8 going to Logie "0". Tas TO8 signal combined with the WRUP signal to 10WRS enables the LED BAR driver shife register D541 to react on input clock signals decived from DUP]. The shift register input data fe applied co the shift register data Anput via the DUPO-Line, Data line DUP2 has a function as "start display" (D2087 Pel2) STDIS and date line DUP3 has a function as “start input” (D2006 Pt12) STINE. 8155 RAM with I/O PORTS and TIMER (02064). The BAM portion 1s organized as 256 x 8 bit and is used as /uP-RAN as described before. (2AM addresses: 6000H ~60FFH). ‘The 1/0 portton consists of the three general purpose I/O ports A, B and Cy (1/0 addresses: PORT A 7O01M / PORT B~ 7002H / PORT C ~ 7003H). A 14 bit programmable counter/timer is included to provide pulses for the TIME/BASE systen, and its timer aodes are prograumable, Input ~ TIMER IN Output - TIMER OUT (TTR addresses: 7004H for the LSB and 7005H for the NSB of the internal Count Length Register. The command/status address is 700CH. IEEE option Communication with the IEEE interface option is done via the @ data/address lines DUPO ..++ DUP7. Tae address selection signal for the interface is signal 0B watch is active in the address range EUOOH and higher.344 3673s Adaption cireuit (unit A9 - diagram 9) ‘The DELAY LINE output is coupled to the ADAPTION UNIT 49, Depending on the selection of MEMORY OFF or MBHORY ON the signal is applied vie the so-called "analog signal path" or the so-called “digital signal path". Selection of the analog signal path (MEMORY OF?) means that the DELAY LINE output is directly coupled to the input of the FINAL ¥ AMPLIFIER via reley-contacts XJ701 and K1702. Signal SHAE is then + 12v. Selection of the digital signal path (MEMORY ON) means that the DELAY LINE output is coupled to the ADAPTION cireuft and then to the MIN/MAX unit. ‘The DELAY LINE 1a terminated by resistors R1704 and R1706. With SHAR = 412V transistors V1707 and ¥1708 are conducting, thus coupling the DELAY LINE output signals to the MIN/MAX unit inputs.BT ee Min/max cireutt (unit Al - diagram 10) If no MIN/MAX mode is selected (signal MIN/MAX = 0) the DELAY LINE is coupled via amplifier stage 2901 to the transistors V2517 and v2518 of the common base circuits before the output CHERRY-HOOPER stage. With MIN/MAX selected (signal MIN/MAX = 1) the DELAY LINE is coupled via auplifier stage D2501 to the transistors ¥2504 and ¥2506 of the coamon base circuits before the CHERRY-HOOPER stage consisting of transistors 02502. From here the signals are applied to the MINimun and MAXimum peak detectors D2503 and 02504, ‘These circuits determine the minimum and maxinun amplitude of the analog input signal during two periods of the sampling frequency, The resulting MIN and MAK values are applied to a MIN/MAX multiplexer consisting of the two circuits D2507 and D2508. _ The MIN value only appears at the output of D2507 when signel HIP ts active and the MAX value appears at the output of 12508 when signal HAP is active. ‘The output of the MIN/MAX multiplexer is coupled to transistors ¥2517 and ¥2518 of the output stage. At the end of each cycle the peak detectors are resetted by pulses RESNIN and RESMAX (see timing diagram). The resulting analog signal MIN/MAX OUT 1s applied to a track and hold (TaH) gate 02092 and then digitized in an Analog to Digital Convertor (ade) 02112 on logic unit ALL. FIG. 3.11, Min/max timing diagram + peak detector.3.463.48 3.7.5. Input/display cireult (unit All ~ dtagram 11) Analog to digital conversion, ‘The analog signal to be digitized is applied from the MIN/MAX cfreultry to a track and hold gate (161) 02092. ‘This TH gate tracks the input signal continuously and at a command TRACK its output is held to the momentary value of the input signal. Signal TRACK is generated in the ADC logic. TRACK = logic "0" The circuit only tracks the iaput level, TRACK = Iogic "1" The circuit holds the input level that was present at the positive going edge of the TRACK signal. (= HOLD). ‘The T&H output signal THOUT Le applied to the ADC input (DZ112-Pt16) and gust be held to the same value at least for che time that is needed by the ADC for conversion (the so-called conversion time of about 450 ns.). It is converted tnto an &-bit digital number. (ADCOO tes ADCO?) The ADG needs a reference voltage of about 0,5V + 0,5%. This VREF voltage can be measured on testpoint X2027 and can be adjusted with potentiometer R 2086. Conversion is controlled by the 10 clockpulses CLADC and by the signal STADG (start ABC) which are generated in the ADC logic. After the first clockpulse the ADC switches the BUSY-signal to logic oid At the end of the conversion of an input signal sanple into 8 bits digital Information, the ADC switches the signal BUSY to logic "0" again, thus indicating that conversion is completed. ‘The ADC output signals are applied now to tri-state buffer D2111. they are also connected to the ADC OUT connector X10 on the rear panel of the instrument. ‘The timing of the conversion is determined by one of the following three sources: 1. In DIREC?-mode by the TIME-BASE GENERATOR, (5 6/dive «++ 0,2 ms/div.) 2, In SAMPLING-node by comparing the analog time-base sawtooth signal and a statrease signal DACSTAIR, (100 jus/div. 0,1 jus/ div.) 3. 1% ekTERNAL“CLocK-mode by the external clock input on the front panel. At the end of each conversion, the ADC logic generates the positive going edge of the TRACK signal. This means that new data ts ready. The TRACK signal is applied to Pt LL of flip flop 02077. The setting of this flip flop results in signal NDA (new data ready) going to logic "I". Now the conversion ritn has to be synchronized to the read/write rite of the pretrigger memory. This 1s done by the TRIGL flip flop. ‘The MEMORY WRITE LOGIC derives from each NDRI, signal a pulse WEPTR (write enable pre-trigger). This circuit detects whether an NDR ts present _or not. With WEPTR the tri-state buffer D2IL1 is enabled with as result that the ADC output bits are placed on the PO ...P7 pretrigger memorya spore rw. Ey rs 3 a FIG. 3.12. 16H gate. 2 on oa 349) T&H GATE Mat i283350 Gatabus system. This digital number is then stored {n the PRE-TRIGGER MEMORY at an address Location which is determined by the PRE-TRIGGER counter. ‘The combination PRE-TRIGGER COUNTER / PRE-TRIGGER MEMORY f LATCH functions like @ digital shift register with a variable Length. The length is directly depending on the front panel pre-trigger setting given by the operator. Depending on this setting which varies between 0 - 1/4 - 1/2 - 3/4 and 1 the length of the shift register will respectively be 0 ~ 1024 ~ 2048 ~ 3072 or 4096 locations. This variable length is teached by varying the count length of the PRE- ‘TRIGGER counter which generates the input addresses for the PRE- TRIGGER MEMORY. (APCO .., APCIL)« FIG. 3.13. Trigger positions on C.R.T. display. The PRE-TRIGGER counter ts presetted to the required value by the nicroprocessor systen with address COO! ond the signals TOUR and PRIRO ~ PRIRI and PRTR2. [Baier vegiater length: [Preset value: [PRIR2TPRIRI| PRTRO 7 FER TTI o 1024 coor afi io 2048 8008 1 | 0) 06 3072 400K o}iio 4096 0008 ao {ojo ‘The PRE-TRIGGER COUNTER can be loaded in two different ways with command JOADPC (load pre-trigger counter). 1) The counter can be losded with the value of PRTRO ~ 1 and 2 at the moment that the counter has reached the state 4095. Loading is carried out via the carry signal on point 15 of the lest counter 02039, 2) During TOWEC, the load signal TOADPC will be generated. TOWKC switches D-flip flop 02043 output Pt 5 to "WG" curing the generation of the signals PRIRO - i and 2. Signal FOLDOFF is also "0" then. After TOWRC the LOADPC signal can gt longer be generated in this way. The firet WEPIR pulse on the clock input of D-type flip flop 04043 Pr 3 switches this flip flop to logic "1" so that signal LOADPC only can be generated via D200¢. Incoming triggers are suppressed until the PRE-TRIGGER COUNTER reaches for the first time the state 4095 after loading on TOWRC by the uicreprocessor. This is done via the signal HOLDOSF when it is active Plow.361 Suppression is stopped when the PRE~TRICGER COUNTER has reached for the first ttme the state 4095 and RW goes to "I", HOLDOFF is switched to "I" thus enabling the trigger flip flops D2077 and D2084 to react on a new incoming trigger. PRE*TRIGGER-MENORY digital shift register with variable length: res I Nn oro Li + oa poco cee | cs Pye cor ji Loe + wo aa po------ coon i " Ly» cur tp bo-- Et 2088 as r--- ao jw [p—m our 3h Lj wa ae te a7 Lp—» ours ° we 5 “az Ba Bie ee FIC, 3.14, Vardable Length of the pre-trigger memory/counter. After storage of a digital oumber in the PREWTRIGCER MENORY with signal WEPTR, the PRE-TRIGGER COUNTER 1s increased by one on the positive going edge of WEPTR.This means that now the next PRE-TRIGGER MEMORY location is addressed and that is the location in which the oldest signal value since the Jast WEPTR is stored. Now the oldest signal sample can be written into LATCH D2109 by means of signal LDTR (Latch delayed trigger). So the LATCH D2109 can be considered es the output of the PRE-TRIGGER MEMORY shift register system. ‘The PRE-TRIGGER MEMORY itself consists of two chips which are selected with signal APCII as chip select sfgnal. APCL] = "0" —> RAM I (12103) OOOH ~ 7FFH APC] = "1" ==> RAM IL (02091) 800i - FFFE On receipt of an Input trigger the shift register output (LATCH output) is coupled to the input of a DISPLAY MEMORY (D2103, 02091) of 4096 x 8 bits. From this moment the MEMORY WRITE LOGIC derives not only WEPTR pulses from the NDRL signal but also WEDSP pulses (Write enable display) for the DISPLAY MEMORY. ‘The DISPLAY MEMORY location in which the PRE~TRIGGER MEMORY output information is placed depends on the state of the WRITE COUNTER, of which the outputs are commected to the DISPLAY MEMORY via a multiplexer D2022,02037 and 02058. The counter starts counting WEDSP pulses at the trigger moment. Counting is done. from the 0 - stare to the state 4095 after which che trigger logic is resctted. The system can react then on a new trigger, after which the DISPLAY MEMORY can be refreshed again. In this way digital numbers are shifted continuousty through the PRE TRIGGER MEMORY shift register system with variable length, at the trigger moment this shift register will already contain information froa before the trigger moment. ‘This information ( a variable number of samples) is first shifted into the DISPLAY MEMORY and then followed with “after trigger” samples until the DISPLAY MEMORY is filled completely. EXAMPLE rmscer MOMENT nsoRwaTion Inscenarion Eiagaty STORED mi THE Which 35 STORED GUetagogres ar wie Wien THe TRIotee ‘eigber MOMENT oven FIG. 3,15. Prectriggering.WEDSP pulses are generated in the following way: 1) WEDSP is derived fron WRUP in case of microprocessor control (URGONT = "L"), (For CLEAR or the use of the TREE option). 2) A WEDSP is generated in case of no microprocessor control (spcont = "O") and after a trigger when NDRL and TRIGL are logic "I". Furthermore generation of WEDSP pulses depend on selection of NORMAL-mode of COMPARE~mode and SINGLE-channel, DUAL-channel or FOUR-channel mode. In NORMAL-~mode points 3 - 11 and 12 of NAND 02032 are nade "1" by the signals CS ~ CR and CQ. The counter outputs AWCO - ANCL and AWC2" are then not active in this cfreuit. In COMPARE-node one of the three WRITE COUNTER output bits ANCO...-AWC2 can be applied in an inverted of _non-inverted way to the inputs of NAND 02032 to suppress the WEDS? pulses, depending on the situations: SINGLE channel DUAL channel FOUR channel and ODD or EVEN This is done under the control of the “microprocessor generated" signals OQ, OR, CS and CT. ogfex[esfor 0 [0 | [oO | Normal-node Yor 0 Jo fo Jt | xormai~node © fo {1 Jo | single channel ~ conpare ~ odd © fo |i Jt | Single channel ~ coapare ~ even 0 |1 Jo Jo | dual channel ~ conpare ~ odd © |1 o |i | oat chanael - compare - even conpate oft ji jo | — oft fifa t— 1 Jo Jo Jo | Four channel ~ conpare - odd 1 Jo Jo |i | Four channel ~ compare ~ even 1 jo fa Jo | — 1 fo fi fa f= 1 |r |o Jo | — afi fo fr | a |i | fo | eh pb f= Storage of samples in display memory. Nornal-node AAAAAAAA Single channel (Channel A) BBBBBBBS Single channel (Channel 3) ABABABAB Dual channel (Channel A and B) ABCDABCD Four channel (Channel A, B, © and D)358 Compare-node. & > > > > ie > ie > > Single chennel (Channel a) les Iso Is 2 Ie Single channel (Channel 5) > ne > te ie Dual channel (Channel 4 and B) b> ie to 2 auxiliary channei (Channel A, B,C and D) In ODD the under Lined sanples are fixed and in EVEN the other senples are fixed. opp cr= 0 EVEN cr= 1 Write counter state Mourunne awc2* — awcI® —awcO —| AWC2R ANCL ANCOR beer oooe HHoerHoo Herorore osrHoore opp r= 0 EVEN cT=1 Write counter state SoUr RAS Awc2e* awcis* awcos* | AWC2** AWCLA* ANOO* cQ=1cR=0 C=O CQ=1 CRO CS=0. Four Four ocoorree358 opp VEN cr = 1 Weite counter state awezt* ancl awco#* | aWG2A® avCL™ ARCO* como Ret cs20 coro RL CSO Dual Dual ° 1 1 1 1 o 1 1 1 1 1 1 0 1 2 1 o 1 1 1 1 3 1 0 1 1 1 1 4 1 1 i L o 1 5 1 1 1 1 0 1 é 1 0 1 1 1 1 7 1 ° 1 1 1 1 opp creo EVEN cr= 1 Write counter state aucze* ancl awcoMe | ANCOR AWCLAR AKCOE ceo CRO CSI cqeo oR cI Single Single ° 1 1 1 L 1 o 1 1 1 ° 1 1 1 2 1 1 1 1 1 0 3 1 1 ° I 1 i 4 1 1 1 1 1 0 5 1 1 ° 1 1 1 6 1 : 1 1 1 0 7 1 L ° L 1 1 { 0 --> WEDSP suppressed. | {1 --> WEDSP generated, CLWC (clockpulse for WRITE COUNTER): ‘The WRITE COUNTER is increased by one with signal CLC. CLHG is generated if all signals NDRL and TRIGL and WR are active, Loading the WRITE COUNTER is done synchronously with a clockpulse CLC derived from LOADS.WR. NDRL latch: Hach TRACK signal is latched in a D-flip flop D2077 of which the output point 9 goes to "I". This circuit detects whether an NDR is present or not. The information is clocked in a second D-flip flop with clocks{gnal CONTC2 to synchronize the conversion ritm to the read/write ritm of the pre trigger memory. This results in NORL (NDRL latch) going to Logic "I", The first D-flip fiop 1s resetted on leading edge of the NDRL signal and the second D-flip flop is resetted with signal CONTC3.356 TRIGCER Latch: As long as triggerpulses TRIG are generated, the output TRGRD of retriggerable one shot D2119 will be logic "1". This output will be switched to logic "0" ff for a perfod of about 100 ms no trigger pulses appear. Signal TRGRD is read by the microprocessor system. Signal TRADT (trigger eutomat) used as clockpulse for D~flip fLop 2077 can be generated in two ways: 1) Instrunent is triggered and not set in AUTO-mode: Signal TRGRD has then a logfc "1" Level and RW used as artificial trigger is then enabled by signal HTRG from the microprocessor to generate TRAUT. ‘The TRIG pulses can set now the D-£lip flop 02077 (Pt 5 —> logic "1"), 2) Instrument is not triggered and set in AyTO-node: When no trigger signals TRIG are generated, signal TRGRD will be logic "0". With AUTO=node selected, the signal HTRG will be switched to logic "I" by the microprocessor, HIRG together with RW results then in signal TRAUT which can set the D-flip flop D2077 to carry out the AUTO function. The flip flop output information can be clocked into a second D-flip Flop D204 on the positive going edge of the NORL signal resulting in signal TRIGL going to logic "1". In this way the incoming trigger is synchronized to the menory read/write cycle. Both flip flops can be reset in two ways: 2) As long as the signal HOLDOFF is low, So from the moment of loading the PRE-TRIGGER COUNTER untill for the first tine the state 4095 is reached. b) As long as signal FINP (End input) is active (logic "1"). During EINP (end input) active (Pt 9 of D2006 is 0") which is read by the microprocessor, the microprocessor is able to clock the value of DUP3 (enable trigger) in the D-flip flop using TOWRE as clocksignal to start a new input cycle. Via OR-circwit D2033 (4-5-6) the flip flop clock input will be blocked directly during an input cycle. The flip flop enables the trigger latch to react on a new incoming trigger and is really active at the end of the holdoff period. EINP is activated again at the end of 2 DISPLAY - MEMORY input eycle with signal LOADS. ZINP is then read again by the microprocessor which then can start a new input cycle. Between the D-type flip flop 2077 and the TRICL D-type flip flop 2084 a circutt is inserted by which is determined that channel A samples always will be stored on even addresses in the DISPLAY MEMORY (starting with address 0000H).Ss A B A B AB in DUAL ch.-mode ad oA Bf DOA in FOUR ch-mode cuanton _[eh.B on ch. on —-in DUAL ch.-mode cxanbon Jeb oalch.c onfehsD onlch.A on[~——in POUR ch.-mode With no MIN/MAX selected (MIN/MAX = "O") signal CHANBON will together with the logic "I" level of signal TRRES determine the moment on which signal TRIGL is switched to logic "I" after the appearance of a trigger signal, Flip flop TRICL is switched on the posttive going edge of NDRL. With MIN/MAX selected (MIN/MAX = logic!1") signal CHANBON will be overruled. Signal TRRES only, determines now the monent of svicching of signal TRIGL. Flip flop TRIGL is switched on the positive going edge of NDRL. After the setting of the TRIGL flip flop, this flip flop is hold in this position with signal TRICL via NAND D2067 (11-12-13). on receipt of an input trigger the PRE-TRIGCER MEMORY output is coupled via LATCH D2109 to the foput of a digital DISPLAY MEMORY which consists of 4096 locations of 8 bits. The LATCH is disabled under microprocessor control when UPCONT = " ‘The LATCH will be enabled If no mictoprocessor control, so when UPCONT = "O", and if WEPTR is active "0". If enabled, the output of the PRE-TRIGGER MEMORY shift register system can be latched into this LATCH. This is done under the control of signal LDTR (Latch delayed trigger). In sequential sampling mode LDTR is steady "I" so that the LATCH is transparant. There is no pretrigger possibility in sequentiel sampling mode. There are three ways in which the DISPLAY MEMORY can be addressed: 1, Generation of addresses AWCO ... AWCL1] by a WRITE COUNTER for wetting new signal information into the MEMORY. 2. Generation of addresses ADCO .., ADCI1 by a DISPLAY COUNTER for reading the contents of the DISPLAY MEMORY to display it on the C.R.T. screen. 3. Generation of addresses AUPRO ... AUPBI1 by the microprocessor system via tri-state buffer (D2122-D2127) for writing and reading when using the IREE ~ option and for the CLEAR function. Selection between addresses generated by the microprocessor or by one of the counters is done by signal UPCONT which is applied to the enable inputs of the MULTIPLEXER (02022, D2037, 02058). UPCONT = "0" means: WRITE COUNTER or DISPLAY COUNTER selected. UPCONT = "1" means: Mictoprocessor generated addresses can be selected.358 Ti no wieroprocessor control, selection between the WRITE COUNTER or the DISPLAY COUNTER is done by the MULTIPLEXER circuit consisting of 2022, 2037 and D2058 which is controlled by the signal MUX. MUX = "I" means: DISPLAY COUNTER selected. MUX = "0" means: WRITE COUNTER selected. WRITE COUNTER (02023, B2038 and D2059) During the process of writing new signal information into the DISPLAY MEMORY the menory location in which information has to be stored is determined by the state of the WRITE COUNTER. Depending on the selected TIME/DIV switch setting the system functions in one of the three modes DIRECT, SAMPLING I or SAMPLING II. DIRECT and SAMPLING I - mode In DIRECT-mode as well as SAMPLING I-mode (0,5 s/div. «+. 0,2 us/div. respectively 5 us/div. +++ 0,1 jus/div.) the counter state is increased step by step with sighal CLC. This process starts with counter state 0000. Signal SEQWC (sequence write counter) is logic "0" in these modes and the counter i.c.’s are switched as follows: rence ME ruse ca] ms kei | | | Mux cc —mf coe — of cue — ef oy ep ON wT 2 RoMs8 mf 1 2 3 WRITE COUNTER 2023 | RCD czas | RoI gp paosa | ROMs. caRRY our FIG. 3.16. WRITE COUNTER in SAMPLING I mode. The counter counts to state 4095 and is then presetted to the zero- state, In SAMPLING I ~ mode DACSTAIR makes one step per sawtouth signal. 4096 sweeps are needed to build a complete picture on the C.R.T. screens359 SAMPLING Ii-mode. in SAMPLING II ~ mode (100 jus/div. sse6 10 jus/div.) the signal SEQuC is switched to’ logic "I" by the microprocessor. The WRITE COUNTER i.c.‘s are now connected together in an other sequence by the microprocessor. Counting ts then done in steps of 256. seawe= "1" mux = news roms Rey ao * | mux cave cone cute ap sya if u 724 news 1 2 3 re sux WRITE COUNTER 2023 | Ace! 2038 fe “ zose | OMSE AREY OUT $59 eb 7 sous FIG, 3.17. WRITE COUNTER in SAMPLING IT mode. In SAMPLING IL - mode DACSTAIR makes sixteen steps per sawtooth signal, 256 sweeps are needed to build a complete picture on the C.R.T. screen. ‘The countsequence of the counter is now: 0, 256, 512, 768, sseeeeeeee 38409 (at Ist sweep) Coy as7, 513, 769, ++ 38414 (at 2nd sweep) 514, 2, 258, ++ 38429 (at 3rd sweep) 770, ++ bn255, 511, 767, 1023, ssesseesee 4095 (at sveep 256) In all modes DIRECT, SAMPLING I and SAMPLING IL the counter will be presetted to the 0 - state when the counter state 4095 is reached. For this a signal LOADS is derived from the carry output signals RCL or RCMSB via D-flip flop 02006. ow JL Lr we ee ee cone LA o.unar o 2e08 ee ee ee tons TL FIG. 3.18, Loading of the WRITE COUNTER.360 DISPLAY COUNTER (D2021, 02036 and D2057) ‘The location in the display memory of an input signal sample which has to be displayed on the C.R.T. screen at a certain moment is determined by the state of the DISPLAY COUNTER. This counter is connected to the address inputs of the DISPLAY MEMORY via MULTIPLEXER 02022, D2037 and 2058, A display cycle is started by the mictoprocessor system via signal DUP2 (enable display counter). The value "1" of this signal is clocked into the D- flip flop 02087 using signal fOWRS as a clocksignal, After this the flip flops clock input is disabled by its output signal vis OR-cArcutt D2033 (8-9-10) The second D-type flip flop D2087 is switched now on the first negative going edge of the signal TRSHXY. After the presetting of the counter with the value of STADO, 1, 2, 9% 10, and 11 the counter starts counting CNTUP (Count up) pulses until the state 4095 is reached. Note that CNIUP pulses can be generated in different ways depending on the selected modes SINGLE channel, DUAL channel or FOUR channel. ‘The output carry signal of the counter (state 4095) is applied via an fnverter D2062 (anti glitch circuit) and AND-circuit D20i8 to the RESET taput of D-f1ip flop D2087. This flip flop is resetted then and resets In turn the next D-flip flop 2087. The signal DT (pulse for display timing) which was logic "1" during display is switched to zero now, indicating that the end of the display cycle is reached. At the sane moment ZDICRT will be resetted (switched to "O"). As long as Z2DTCRT is logic "0" the C.R.T. beam will be blanked. The microprocessor is elso informed about the end of the display cycle by reading signal DT. or arsPLay | BLANKING Leno oF viseuae FIG. 3.19. Display timing. With eignal DT logic " the counter can now be presetted again. DISPLAY COUNTER in KEMORY-QUARTERS ~ mode. Im MEMORY - QUARTERS ~ mode the DISPLAY COUNTER can be presetted again at the end of the display of the selected QUARTER (D2007). Presetting is done by the microprocessor systen via the signais STADO- 1-2 and STAD9-10-11 (Start address display counter) according to the following table.361 10 9/8 7654 3/210 11 povolp pvdov pb pip vv AA AIA AAA A ALARA START vit: treet ttre quarters s s|s s § § § 8/5 5 8 0 9 Of0 9 0 0 0 O/0 O 0/ 000K < Preset value oo o}t 22 a1 aft a i)iree 1 o 9 t]o 9 0 0 O of 0 0] 200K <- Preset value oo aft tar. afi. a] aR 2 i < Rnd of Quarter 1 2 1 0/0 0 0 0 0 Of0 0 O| 400K < Preset value o1 oft ti ud aia tt) sek 3 <- End of Quarter 2 © 1 1/0 0 0 9 O O10 0 0} 600K <- Preset value Ori}, 22 rt ifr a ilar 4 ' <> End of Quarter 3 10 010 0 0 0 0 0]0 0 0} 800K < Preset value root tar 2 ifr a 1] 9rre 5 < End of Quarter 4 12 0 1/0 0 6 0 0 o|fo 0 0) aGoH < Preset value roujt tata rir i 1] seen 6 ' < End of Quarter 5 1 1 0/0 09 0 9 0 0]0 0 OJ coon < Preset value rrol: trata air a tforew 7 <> End of Quarter 6 2 11/0 0 000 ofo © of goon baaijr trait a}. ti] epee + < End of Quarter 7 ‘The table shows that the display counter bits STAD3 ... STADS always "0" when presetting the display counter. ‘The ends of each of the seven quarters are decoded by exclusive - OR circuit 2099 in the following way: saps | aves [Tr9 HHoo 80: nd is reached when signal TI9 is gotng from logic " a) When startaddress bit STAD9 is set ¢o logic “0! and DISPLAY COUNTER output ADC9 is going from logic “1" or b) When startaddress bit STAD9 is set to logic COUNTER output ADC9 ie going from logic "0" to logic " Logie "and DISPLAY In QUARTER-mode (QDR = "O") the D-flip flop D2007 functions as inver~ ter of signal TI9, At the end of the selected quarter a second D- £lipflop D2007 is switched by TI9 and a preset of the DISPLAY COUNTER is given then, At the end of a display cycle the Z-control is switched such that the display 1» blanked via signal DT which is going to "0" then.362 MULTIPLEXER he multiplexer consisting of 02022, 02037 and 2058 is switched in tri-state under microprocessor control (UPCONT = I"). If no microprocessor control (UPCONT = "O"), the multiplexer vill be enabled and will select the WRITE COUNTER ourputs AWCD ... AWCL1 oF the DISPLAY COUNTER outputs ADCO ... ADCLI depending on the level of signal MUX. MUX = 1 -> DISPLAY COUNTER selected. MUX = 0 => WRITE COUNTER selected. AVSB and Quarter LOGIC et ode (AVSB = 0") Horizontal deflection ‘The DISPLAY MEMORY address tnformation ADCO ... ADCIL from the DISPLAY COUNTER is clocked om signal LXDA into multiplexer D2019 and latches 02034 and 02056. Furthermore latch D2069 is switched in tri-state. a) No DISPLAY QUART selected. Pr Muleiplexer 2019 1s switched by control signal QDR in such a way that signals ADCO ~ ADC] ~ ADC2 and ADC3 are placed on the XDACI bus. Latch D2056 is enabled and Latch D2034 1s switched in tri-state which results In placing the signals ADC4 .,, ADCI1 on the XDACE bus. Signals ADCO ... ADCL1 are now applied to the horizontal DIGITAL, 10 ANALOG" converter XDAC as XDACIO ... XDACTI1. Ynis will result in a signal XDAC for horizontal deflection. Ret DISPLAY MEMORY ERT. SOREEN nine FIG. 3.20. Display without DISPLAY QUART selection. b) DISPLAY QUART selected. BBR = "0" In DISPLAY QUART - mode only a quarter of the DISPLAY MEMORY contents has to be displayed. The address input information for the XDAC must be multiplied now by a factor of 4 to display this quarter over the whole 10 divisions sereen width.263 TDR et DISPLAY MEMORY Tomah \WITHOUE MULTIRUING Br urs surbure eee By SHIFTING THE sina S acy ao HO BITS FIG, 3.21, Display with DISPLAY QUART selection. This is realized if QE = "o" by shifting all the bits ADCO s+» ADCLL two bits to the left with the ald of multiplexer 02019 and Latches D2034 and 2056. _ Multiplexer 02019 is switched by control signal GOR in such a way that signals "0", "0", ADCO and ADC] are placed on the XDACT bus. Latch D2034 is enabled and Latch D2056 is switched in tri- state which results in placing the signals ADC2 ... ADC9 on the XDACT bus. Signals ADCO... ADC9 and two tines “o" for the two L.s.b.’s are now applied to the horizontal "DIGITAL TO ANALOG" converter XDAC as XDACIO ... XDACIIL. In this case bit 9 has to be inverted to prevent the system from starting with the display of the signal in the centre of the screen. ‘The offset of the operational amplifier D2070 can be adjusted with potentiometer R2052. Vertical deflection In Xt - mode the same signal value ig stored in latches 2128 and D2123 with LYDAL and LYDA2. Both informations are applied to an adder consisting of D2124 and 02129 and added to each other, ‘The output of the adder (shifted one bit to the left) is applied to the vertical digital to analog converter YDAC. With this shifting of one bit of the adder output this output value is divided by a factor two again, In this situation the lowest adder output bit will be steady nom, ny fyi mode (AVSE Hortzontal deflection The stgnal path DISPLAY COUNTER --> XDAC is now blocked. Signal information from channel A in now placed on the 8 highest Input bits (XDACT4 ... XDACTIL) for the XDAC input via tri-state304 latch 02069. This latch is enabled by AVSB = "1" and the data is clocked in this latch with signal LXDA. ‘The four lowest input bits for the XDAC are then connected to Yo", This is realized by signal BT by latching the state of the display counter in lateh 12019 before the start of an AVSB display cycle. Latches 02034 and 02056 are ewitched in tri-state. Vertical deflection The channel B data will now be offered to the YDAC. One signal value is clocked into D2iz8 with LYDAL, the next signal value is clocked into D2123 with LYDA2 andthe next again {nto D2128 with LYDAI and so on. in this way there are always two adjacent channel B signal values available at a time and they are applied to en adder con- sisting of D2124 and D2129 and added to each other, The output of the adder (shifted one bit to the left) is applied to the ver~ ticel digital to analog converter YDAC. With this shifting of one bit of the adder output this output is divided by a factor two again, This results in an average signal value on the YDAC input. In XA / YB~ node Lt is possible that the lowest adder output bit will go to logic "1", This information is added to the YDAC output signal via an adjusting network, to correct (round off) the output signal. Round off in aVSB-mode can be realized by ad~ justing potentiometer R208¢. Communication with ISEE option. The DISPLAY MEMORY can be addressed via the AUPBO . system. (UPCONT = "I"). Data communication ts done via the DO ... D7 bus system. AUPBII bus MULTIPLEXER 02008 This muleiplexer controls not only the WRITE COUNTER but generates also the signal SALT (Sequential alternating). SEQNC "L" —--> Signal SALT equals signal TRIGL. (SAMPLING TT - mode ). SEQWC "0" ——-> Signal SALT is steady logic "I". (DIRECT + SAMPLING I'- mode ). MULTIPLEXER 02088 This multiplexer generates the signals DATUPC, OBCONT, OFDM and TATEN depending on the level of signal UPCONT which is generated by the microprocessor. | partrc|aecont UPCONT = "1" DAT nye367.8. 265 Gonteol logic (untt All ~ diagram 12) PRASE LOCKED LOOP 4 20 Miz signal is needed for different functions inside the instru- ment. This 20 MHz signal 4s derived from the 2,5 Mz clockpulse output from the ya Processor by aeans of a voltage controlled oscillator (VCO) 2168 that has an output Frequency of 40 Mi To obtain this stable VCO output, the 40 Miz output signal is divided by a factor of 16 with the afd of flip flop D2098 and counter D2107. The resulting 2,5 Mz signal (FEEDBACK signal at point 3 of D2108) is then compared with the reference signal of 2,5 Miz of the microprocessor clockfrequency at point 6 of D2108 in a phase detector, which is used to control the YOO frequency. The cireuit can be locked with potentiometer R2044. CONTRO, COUNTER ‘The control counter which is needed for timing purposes counts 20 Miz pulses, The control counter {s presetted to the value 1011 (11) at the moment that the counter state 0100 (4) is reached and the next count pulse appears. The next counting cycle is then started, is ahi ‘ conrcy pacer ere | of ra <| | H 1 sonics gage rt | of ‘ I conrea ovver riz LO Je i I conta 9 2m02 ery |? aft | t I i 0 aoe er a ' ‘ PRESET MOMENT 4 FIG. 3.22. Control counter timing diagram. A number of timing signals CONTC] ~ CONTC2 ~ CONTC3 = RW - MUX ~ OE and WR is derived from the control counter output signals. Signal RW determines the time in which new data can be written in the DISPLAY MEMORY or in which data can be vead from the DISPLAY MEMORY for display. w= "1" means: WRITE (data input) RK means: READ (display) See the timing diagram. Count pulses (CNIUP) for the DISPLAY COUNTER Depending on the selected mode 1 ~- 2- 4 or 8, CNTUP pulses will be generated per LYDA (Latch Y DAC) cycles366 ‘The CNTUP cireult consisting of D201 + D2029 is progranmed by the poe via the signals STA (Step A), STB (Step B) and STC (Step 6). Mode steps sta | stp | src SINGLE step 1 1 1 1 DUAL or STNGLEHCOMPARE Step 2 1 1 0 FOUR or DUALFCCMPARE, Step 4 1 0 6 FOUR and COMPARE Step 8 0 0 0 See also the timing diagran! Latch enable afgnals LDA, LYDAl and LYDA2 for the horizontal DAC (Ac) and for the vertical DAC (¥DAC). Signals LKDA, LYDA1 and LYDA2 have to be generated only during a READ cycle when signal RD = logic "I". This is done in a different way for the X=t and the X#A/Y=B modes as shown fn the tining dtagram. The multiplexer D2073 in the circuit where the latch enable signals are generated ts functioning according to the tabel below. Position of multi=[Control Inputs [output Pe T[Output Pe 9 plesee D2073. [AVSE""TADODE"| 9 o | o | x etl i} ker 1 0 1 | oem Rr 2 1 o | 0 er 8 wea 3 1 1 | on a 02073 4s only enabled when signal RT2 is logic "2". DER LDTR is the lateh enable signa? for the LATCH D2109. - This signal is in DIRECT-mode (DIR = "0") always derived from signal Ds = Signal LDTR is always Logic "1" in SAMPLING~mode (DIR = 1"). BLANKING CTRCULT This circuit provides for a blanking signal ZMOD (2-modvlation) for blanking the trace on the C.R.T, display. This ZMOD signal feactions only in MEMORY ON mode when signal STORE is active (logic "1"). 2MoD = logic "L" means: unblanking 2MOD ~ Logic "0" means: blanking ‘The trace on the C.R.T. screen is oaly preseat if all the input signals of NAND circuit 92029 (1-2-4-5-6) are logie "1" at the same tine. - pin 5 ZEN + The signal ZEN (Z-enable) is generated by the nictaprocessor, ~ pin 4 2DTCRT : This signal is active during a display cycle.367 Signal TRSEXY. ‘his signal is generated for deglitching of the DAC. FIG, 3.23. Deglitching of the XDAC. CHOPPER LOGIC With this cfreuft the signals CHOP1 and CKOP2 are generated. These signals are used to control the channel selector in a way which depends on the selected modes SINCLE channel, DUAL channel, FOUR channel, MIN/MAX-mode, DIRECT-mode, and SAMPLING T or SAMPLING LI mode. Signal CHOPB is only active in four channel~mode and is always logic "0" in SINGLE- or DVAL-channel-node, srs 1 cata toe PIG. 3.24. Chopper signals in four-channel mode. SINGLE channel. Signal DIGCH is logic "1" in SINGLE channel mode. The analog channel switch is switched in instead of the digital channel switch. This means that the chopper logic has ao function in this node. DUAL chanael and ao MIN/MAX-mode in DIRECT and SAMPLING T-mode: oe ‘espe Lose oe hae Ps 8 IG. 3.25. Chopper circutt. Signal SALT is logic "1" {a DIRECT and SAMPLING I - mode.3-88 Signal CKOP2 is steady "0" and signal CHOP! is switched during each conversion cycle by signal STADC. owe SSL ewe SOLS LS FIG, 3.26. Chopper signals. DUAL channel and no MIN/MAX-mode in SAMPLING IT-mode: oi (HOPPER Lat T PIG. 3.27. Chopper circuit. surfrne vine mon oe = —JSL_f_,E SL = FIG. 3.28. Chopper signals. ‘The circuit functions in such a way that the SAMPLING II-mode cycle always starts with channel A, The trigger eignal on which the SAMPLING II cycle is started, switches signal SALT to logic "0". On the same moment signal CHOP! will be switched to "0" in the following wai If output point 5 of flip flop 02083 1s switched to "1", exclusive= or cireutt D2072 will be switched as an inverting stage. The low level of signal SALT results then in a signal CHOP1 with logic level From the moment that signal SALT 1s switched to logic "0", the CHOPI signal will be switched by signal ROMSB after cach group of 16 conversions. In this way first 16 samples of channel A are stored, then 16 sanples of channel B, then again 16 of channel A and so on.369 DUAL channel and MIN/MAX-mode in DIRECT-mode: + cHoPmER Lot FIG. 3.29, Chopper circuit. cHopl = cr CHOP2 = Logie In DUAT, channel MIN/MAX-mode, the system 16 alternating between chan- nel A and B, This is completely determined by the signal CT from the microprocessor. FOUR channel and no MIN/MAX-mode in DIRECT and SAMPLING I-mode: 1H HorPe Los al , = mi r FIG. 3.30. Chopper circult. Note: Auxiliary channel can never be combined with the MIN/MAX mode! he circuit acts as a simple two-bits synchronous counter, This counter has two outputs CHOP! and CHOP2 and is clocked by the signal STADC. The circuit switches to the next state during each conversion thus selecting the next channel. ¥IG. 3.31, Chopper circuit.370 FOUR channel and no MIN/MAX-node {n SAMPLING TI-node: os oneE 6K syed FIG. 3.32. Chopper circuit. Note: Auxiliary channel can never be combined with the MIN/MAX mode! ‘ r | | wer foe i [71 FIG, 3.33. Chopper signals.FIG. 3.34. Display timing I.373 ” LULL it Lrousrtyt L ek oo om no PL ” 5 L i L a i fr L 5 L r u » 1 I L L I~ L r 1 r 1 fr "7 I 1 r l fF L _S 1 a L I L = L _ U _f L a J 1 r 1 r n aoe ants oY iL nh nh A n wow TU he f fl n n n wor a ine | Hl n fn n ae ST PIG, 3.35. Display timing IL.37676 378 ADG logic (unit ALL ~ diagram 13) Digital time-base generator. ‘The time-base circuit generates a number of signals with different frequencies which determine the sampling/conversion rate, These frequencies are derived from the 20 MHz from the PHASE LOCKED LOOP circuit by frequency dividing. These signals are synchronized with the 2,5 Miz clockpulse output of the microprocessor. The digital time~base functions only in the TIME/DIV switch positions 0,2 ws/div. ... 0,5 s/div, in the so-called DIRECT-mode. This digital time-base is not used for the SAMPLING mode (TIME/DIV switch positions 100 yus/div. «+. 0,1 jus/div.). Encoding TIME/DIV settings, Depending on the setting of the TIME/DIV switch, one of the: frequencies is selected and called TIMER OUT. The relation between the TIME/DIV switch settings and the signal TIMER OUT is such that there are always 400 pulses TIMER OUT per horizontal division. (Not in DISPLAY QUART mode and x10). The digital tine-base consists of a multiplexer D2001, # decimal counter D2012 and a timer (part of the circuit 81552 02064). With the multiplexer a signal CTR with a frequency of 4 Miz is generated, ‘The counter realizes the dividing of the 4 Miz signal by factors :2 / 25 / or 210. Dividing factors of :10 / :100 / :1000 / or :10000 are realized with the tier under the control of the microprocessor. Multiplexer D2001. ‘Timing control counter Te cre pi] cl]ea output Pt. 5 output Pe. 6 {— Hororore Heecence One rroee This multiplexer is always enabled. ‘The aultiplexer which is controlled by the signals (CONTCO, CONTCL, CONTC2_and CONTC3) from the control counter produces the signals CTS and CTS according to the timing diagram below.376 come LL FIG. 3.36. Timing of signal C7B. The settings of the TIME/DIV switch are read by the microprocessor system. The microprocessor in turn loads the counter circuit D2012 via the signals TBC and TBD according to the next table, Setting [Frequency |rso|rec|rat|n2012 | 8155 | 7B10 factor +| factor| factor reload CTIME/DIV number pushed) 0,2 msfdiv.| 2 Maz |i |o}o}2 2000) 1 - 0,5 as/div.|go0 Kez fo ]i}o]5 oil 1 - Las/div.|400 kHz | o| 0] 0 |10 ooo] 1 - 2 ms/div./200 Kaz [1] } 1] 2 1000] 10 - 5 ms/div.| 80 kHz |o]1] 1] 5 ori} 10 - 10 ms/div.| 40 Kaz | 0] 0} 1 |10 coco] 10 - 20 ms/div.| 20 kHz | 1/0] 1] 2 1000] 100 - 50 ms/div.; 8 Kaz [oO | 1 5 101) 100 - 0,1 s/div.| 4 KR | 0 | 0] 1 |10 0000] 190 | 1000 (1s/div.) 1000|1000 |10000 (2s/div.) 0101] 1000 |10000 (5s/div.) 0,2 s/div.{ 2KHz |1 ]o fi 0,5 s/div.[300 Be |O}1 ji Reloading the counter ts done when ripple carry output RC is logic “I and signal CTS is logic "1". The counter is loaded then with a value which is determined by the microprocessor system depending on the current setting of the TIME/DIV switch. Especially for the setting 0,2 ms/div. of the TIME/DIV switch it is necessary to preset the counter only during the time that signal ConTC3 = logic "I" to realize a correct timing far the rest of the cireuitry. (in reality D2093 functions always when TBD = "1"), After loading, the counter will count the 20 Miz input clockpulses, but is only able to do this when the counter is enabled by the signal CTE (of 4 me). In this way the counter counts with a speed of 4 MHz and syachronously with the 20 Miz signal,377 At the mowent that the signal RC ts switched to logic "I", the counter will automatically be reloaded again, In this way a continuous counting process is realized. Dividing by « factor of 2 is done by loading the number 8 (1000) and counting up to 9. Dividing by a fector of 5 is done by loading the number 5 (0101) and counting up to 9. Dividing by a factor of 10 1s done by loading the number 0 (0000) and counting up to 9. The resulting output signal RC is applied to the timer circuit, This timer circutt {s progranzed by the microprocessor system for counting by Zactors of 1, 10, 1000 or 10000 depending on the setting of the TIME/DIV switch position, The internal 14 bit COUNT LENCTH REGISTER of the 6155 can be programmed via two addresses 7004H for the 1.8.3. and 7005H for the M.3.B, 700s l 20004 i]t [re] ta] ri [relze [rs ee pe] ts [re [ra [eT [po 1 4 I FIG. 3.37, 1é-bic count length register. The timer is programmed for automatic reloading and generation of a single pulse everytime TC is reached. In the TIME/DIV switch positions 0,2 ms/div., 0,5 ms/div. andl ms/div. the TIMER OUT signal-path is blocked with signal TBT via NAND- gate D2061. This is done because the timer is not able to divide by a factor of 1, As result of the time~base generator, HOCOND (hold and convert pulse in DIRECT-mode) pulses are derived when SYNCH = "0". In each TIME/DIV switch position in DIRECT-mode 400 HOCOND pulses will be generated per horizontal division, Each HOCOND pulse starts the analog to digital conversion of a new input signal sample. SAMPLING-mode. Depending on the setting of the TIME/DIV awitch, one out of two possible sampling modes is autouatically selected. These modes are called SAMPLING I and SAMPLING IT mode. SAMPLING I mode in 0,1/us/div. Syus/div. SAMPLING II mode in 10pus/div. «.. 100jus/div. Correct functioning in this mode requires that signals of a repetitive nature are applied to the input channels of the instrusent. Each sampling cycle is started with the WRITE counter in the zero position. First the SAMPLING I~mode principle will be described. During one sampiing cycle 4096 samples of the {nput signal are stored in the DISPLAY MEMORY to build a complete signal picture. on each input trigger signal one sample of the input signal is taken in a way as now described.378 In SAMPLING Imnode the WRITE COUNTER will be able to count 4096 WEDSP pulses, For this purpose the counter is configurated as follows. [ttt tttt ttt ot ote ‘SOMPUNG -I- MODE so FIC. 3.38. WRITE COUNTER in SAMPLING T mode. See also the explanation about the functtoning of the WRITE COUNTER. we Le OS. cBinter PEE Shia eee woe LE b tg wie EERE FIG, 3.39. SAMPLING I mode principle. on each trigger signal a fast ramp is generated (by the normal analog time-base generator), which 1s compared by a comparator (D2016) with the output signal of a DAC eireutt DACSTAIR (D2009). ‘The WRITE COUNTER output signals AWCO ... AWCli are coupled to the DAC STAIR. The WRITE COUNTER runs after fllp flop NDRL, is switched by the First active trigger. The counter state is then converted into an analog signal DACSTAIR. The comparator 1s only active in sampling mode. Signal DIR is then logic "0". At the cross-over point determinad by each comparison of the fast ramp signal and the DACSTAIR signal, an HOCONS (hold and convert pulse in SAMPLING-mode) pulse is generated to start the ADC conversion of the new signal sazple.379 The time between the samples depends on the fast ramp speed, which in turn, is determined by the time-base setting. so0ee FIG. 3.40. Fast ramp. After each conversion the WRITE counter state is tncreased by one step, which causes the DACSTAIR output signal to increase by one step. (1 a¥/step on D2024 - pt 6). This can be adjusted by potentioneter R2033 (ampl. staircase). In this way, the time (ts) between the trigger pulses and the generation of the HOCONS signal increases so that each new sanple is taken one step later. Whea the WRITE couater reaches the state 4095, the last sample will be taken and a complete picture will he formed. Avnew sampling cycle can now be started again. ‘COMPARATOR ——k— x4 ao oe » Ye Ocsure soerion seo FIG. 3.41, Comparator,380 The fast ramp sawtooth voltage 1s applied to the positive input Pt 12 of comparator 12016, To the negative input Pt 11, a voltage DACSTAIR is applied. Tf the fast ramp reaches the potential of the preset voltage DACSTAIR, the comparator output HOCONS goes high. D-type flip flop D2052 will be set and HOCONSE will be I", thus {nitiating 2 new conversion cycle. on the inverted output Pt 8 of this flip flop, a negative going pulse appears, which 1s applied via diode ¥2003 and capacitor 62003 to the positive input of a second comparator, which was already on a positive level of 0,7. This results in a negative going pulse on this "+" input. The output Pt 4 of this second comparator’ (with on its "=" input a OV) is switched to "0" and this "0" is applied to the strobe input Pt 8 of the first comparator and via 2012 and C2003 to the "+" input Pt 1 of the second conparator. In this way the output signal HOCONS of the fret comparator will stay high. Output Pe 8 of flip flop D2052 and output Pe 4 of D2016 form an AND function, so as long as output Pt 4 of D2016 is low, the anode of v2003 is low. Capacitor C2003 is reloaded via R201! from the +5V. When input 1 of 2016 has reached + 0,7 V again (duration about 2,4 jus ) output 4 of D2016 ic switched to high and the first comparator can be used again because it is enabled again by the high level on its strobe input Pt 8. This is done to prevent the first comparator from switching more then once for one step made by DACSTAIR. The SAMPLING IL mode principle is now described below. 16 samples per fast ramp instead off 1 sample per fast ramp are digitized in this mode. ‘This means that this mode is lox faster. Only 256 sweeps instead off 4096 are needed to built a complete picture. (trace). ‘The WRITE counter 1s now configured in such e way that {¢ is counting with steps of 16, SAMPLING --MODE. FIG. 3.42. WRITE COUNTER in SAMPLING IT mode.381 See also the explanation about the fumctioning of the WRITE COUNTER. Ei he we — : om OULU FIG, 3.43, SAMPLING TI mode prinetple. After 16 samples the system is waiting for a new active trigger and a new fast ramp to produce the next 16 samples and so on. When the WRITE counter reaches the state 4095 the last sauple will be taken and a complete cycle can now be started again. Note that first 16 samples of channel 4 are taken, then 16 of channel B and 60 on. External. clock logic The conversion ritm can also be determined by the operator by connecting a TTL signal of the required frequency to the EXT CLOCK input socket X6. ‘These external clockpulses are applied to a retriggerable one shot 2119 resulting in a signal EXTCL when the frequency is > 40 Hz. This signal opens the AND-gate D2093 so that the external clockpulses can pass this gate, These pulses can also pass OR-gate D2079 as iong. as the signal HOLD OFF OUT = ogic "O", Tats signal is always "0" in EXTERNAL CLOCK mode, because of signal DIR which is "0" then. For clockfrequenctes < 40 He the one shot D2119 can be switched by means of switch $2002. This 1s an internal switch located on unit All. With 82002 closed, signal EXTCL will be atendy Hold off logic. The HOLD OFF IN and the HOLD OFF OUT signal are the same ta MEMORY OFF mode, seas ad oe FIG. 3.44, Hold-off Logie.382 In MEMORY ON (STORE = "O") and DIRECT-mode (DER = 0") signal HOLD OFF OUT will steady be "0" and the sawtooth generator will be blocked «(Mot in the AUTO - mede). 2 . FIG. 3.45. Hold-off logic. Im MEMORY ON (STORE = "O") and SAMPLING ~ mode the upgoing edge of the HOLD OFF OUT signal is made synchtonous with the triggers, oe FIG. 3.46. Hold-off logic. wo ort LI FIG. 3.47. Hold~off timing. Because of internal drift in the oscilloscope, it can happen in the SAMPLING mode that no HOCONSE pulses ate generated because the sawtooth level is higher than the DACSTAIR level, so that thi comparator will not switch at all, it gives constantly logic the output. FIG. 3.48. Adjustment of correct DACSTAIR level. With the aid of the HOLD OFF circuit a HOLD OFF OUT signal (derived from TRAUT) applied to Pt. 4 of OR-circuit 02079 causes the generation of a HOCONSE pulse to start the SAMPLING cycle,